Texas Instruments manual Mono Mixer Control, Treble Control, 1. TAS3002 Mixer Function

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Figure 4−1. TAS3002 Mixer Function

Left Channel Mix Coefficients		SDIN1 ^ SDIN2 ^ ADC
I2C Register Address 08h		SDIN1 ^ SDIN2 ^ ADC
I2C Register Address 08h
		= (3) 24-Bit Left Mix Coefficient

SDIN1_L

SDIN2_L

L_SUM

7 Biquad

Filters

ADC_L

SDIN1_R

SDIN2_R	7 Biquad

Filters

ADC_R

R_SUM

1/2

1/2

Right Channel Mix Coefficients I2C Register Address 07h

Tone

Tone

Soft

Volume

DRCE

SDOUT1

Soft

Volume

DRCE

L + R_SUM

SDOUT2

SDIN1 ^ SDIN2 ^ ADC

= (3) 24-Bit Right Mix Coefficient

Figure 4−1. TAS3002 Mixer Function

4.4 Mono Mixer Control

The TAS3002 device contains a second mixer that performs the function of mixing left and right channel digital audio data from the input mixer in order to derive a monaural channel. This mixer has a fixed gain of −6 dB so that full scale inputs on L_sum and R_sum do not produce clipping on the resulting L+R_sum.

The output of this mixer is present on terminal 24 (SDOUT2) and is generally used for a digitally-mixed subwoofer or center channel application.

4.5 Treble Control

The treble gain level may be adjusted within the range of 15 dB to – 15 dB with 0.5-dB step resolution. The level changes are accomplished by downloading treble codes (shown in NO TAG) into the treble gain register. Alternatively, a limited range of treble control is available by asserting the treble-up or treble-down GPI terminal (see Section 7.6.1).

The treble control has a corner frequency of 6 kHz at a 48-kHz sample rate.

The gain values for treble control can be found in Section NO TAG.

4−2

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Contents Data Manual TAS3002Digital Audio Processor With Codec 2001IMPORTANT NOTICE 1.1 Description 1.2Features1 Introduction 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram 1.4 Terminal Assignments 1.5 Terminal FunctionsFigure 1−2. TAS3002 Terminal Assignments Table 1−1. TAS3002 Terminal FunctionsTable 1−1. TAS3002 Terminal Functions Continued Page Table 2−1. Serial Interface Options 2 Audio Data Formats2.1 Serial Interface Formats … … … … 2.2 Digital Output Modes… … … … … … … …2.2.2I2S Serial-InterfaceFormat Figure 2−2. I 2S Serial-InterfaceFormat… … … … … … … …2.2.3MSB-Left-Justified, Serial-InterfaceFormat … … … …… … … … … … … …2.3 Switching Characteristics PARAMETERUNIT tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0Page 3 Analog Input/Output 3.1 Analog Input3.2 Analog Output 3.2.1Direct Analog OutputFigure 3−3. Analog Output With External Amplifier 3.2.2Analog Output With GainFigure 3−2. VCOM Decoupling Network Figure 3−4. TAS3002 Reference Voltage Filter 3.2.3Reference Voltage FilterTAS3002 Page 4.1 Soft Volume Update 4 Audio Control/Enhancement Functions4.2 Software Soft Mute 4.3 Input Mixer ControlFigure 4−1. TAS3002 Mixer Function 4.4 Mono Mixer Control4.5 Treble Control Figure 4−2. De-EmphasisMode Frequency Response 4.6 Bass Control4.7 De-EmphasisMode DM 4.8 Analog Control Register 40h Table 4−1. Analog Control Register Description4.9 Dynamic Loudness Contour 4.9.1Loudness Biquads4.9.2Loudness Gain 4.9.3Loudness Contour Operation4.10 Dynamic Range Compression/Expansion DRCE 4.11 AllPass Function4.12 Main Control Register 1 01h 4.13 Main Control Register 2 43hTable 4−2. Main Control Register 1 Description Table 4−3. Main Control Register 2 DescriptionPage Figure 5−1. Biquad Cascade Configuration 5 Filter Processor5.1 Biquad Block 5.1.1Filter CoefficientsPage 6 I2C Serial Control Interface 6.1 Introduction6.2 I2C Protocol Figure 6−1. Typical I 2C Data Transfer Sequence6.3 Operation 6.3.1Write Cycle ExampleTable 6−1. I 2C Protocol Definitions Table 6−2. I 2C Address Byte Table6.3.2TAS3002 I2C Readback Example 6.3.3I2C Wait States6.4 SMBus Operation 6.4.1Block Write Protocol6.4.2Write Byte Protocol Table 6−3. I 2C Wait States6.4.3Wait States 6.4.4TAS3002 SMBus ReadbackPage 7.2 Power-Up/Power-DownReset 7.2.1Power-UpSequence7.2.2Reset 7 Microcontroller Operation7.2.3Reset Circuit Figure 7−1. TAS3002 Reset Circuit7.2.4Fast Load Mode TAS30027.3 Power-DownMode 7.2.5Codec Reset7.3.1Power-DownTiming Sequence Figure 7−2. Power-DownTiming Sequence7.4 Test Mode 7.5 Internal Interface7.6.2GPI Architecture Table 7−1. GPI Terminal ProgrammingFigure 7−3. Internal Interface Flow Chart Restore Volume and MCRStart Power Up Initialize Default EEPROM Slave Write GPI Power Down7.7 External EEPROM Memory Maps Table 7−2. 512-ByteEEPROM Memory Map 2.0 ChannelsADDRESS BYTE NUMBERFUNCTION TAS3002TAS3002 ADDRESS NUMBERFUNCTION CATEGORYTAS3002 ADDRESS NUMBERFUNCTION CATEGORY8.2 Recommended Operating Conditions 8 Electrical CharacteristicsStatic Digital Specifications Figure 8−1. ADC Digital Filter Characteristics 8.4 ADC Digital FilterFigure 8−4. ADC High-PassFilter Characteristics 8.5 Analog-to-DigitalConverter8.6 Input Multiplexer 8.7 DAC Interpolation Filter8.8 Digital-to-AnalogConverter 8.9 DAC Output Performance Data8.10 I2C Serial Port Timing Characteristics Figure 8−7. I 2C Bus Timing9 System Diagrams Figure 9−1. Stereo ApplicationTAS3002 ClockTAS3002 TAS3001Figure 9−2. TAS3002 Device, 2.1 Channels PLASTIC QUAD FLATPACK 10 Mechanical InformationPFB S-PQFP-G48 10−2