Texas Instruments TAS3002 manual 2.2.2I2S Serial-InterfaceFormat, 2. I 2S Serial-InterfaceFormat

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2.2.2I2S Serial-Interface Format

The normal output mode for the I2S serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−2 shows the following characteristics of this protocol:

•Left channel is transmitted when LRCLK is low.

•SDIN is sampled with the rising edge of SCLK.

•SDOUT is transmitted on the falling edge of SCLK.

•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

SCLK

LRCLK = fS

SDIN X MSB

SDOUT X MSB

… …

LSB

…

XMSB

X MSB

… …

LSB

…

Left Channel

Right Channel

Figure 2−2. I 2S Serial-Interface Format

2−3

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Contents 2001 Data ManualTAS3002 Digital Audio Processor With CodecIMPORTANT NOTICE 1.1 Description 1.2Features1 Introduction 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram Table 1−1. TAS3002 Terminal Functions 1.4 Terminal Assignments1.5 Terminal Functions Figure 1−2. TAS3002 Terminal AssignmentsTable 1−1. TAS3002 Terminal Functions Continued Page Table 2−1. Serial Interface Options 2 Audio Data Formats2.1 Serial Interface Formats … … … … … … … …2.2 Digital Output Modes … … … …… … … … 2.2.2I2S Serial-InterfaceFormatFigure 2−2. I 2S Serial-InterfaceFormat … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0 2.3 Switching CharacteristicsPARAMETER UNITPage 3.2.1Direct Analog Output 3 Analog Input/Output3.1 Analog Input 3.2 Analog OutputFigure 3−3. Analog Output With External Amplifier 3.2.2Analog Output With GainFigure 3−2. VCOM Decoupling Network Figure 3−4. TAS3002 Reference Voltage Filter 3.2.3Reference Voltage FilterTAS3002 Page 4.3 Input Mixer Control 4.1 Soft Volume Update4 Audio Control/Enhancement Functions 4.2 Software Soft MuteFigure 4−1. TAS3002 Mixer Function 4.4 Mono Mixer Control4.5 Treble Control Figure 4−2. De-EmphasisMode Frequency Response 4.6 Bass Control4.7 De-EmphasisMode DM Table 4−1. Analog Control Register Description 4.8 Analog Control Register 40h4.9.3Loudness Contour Operation 4.9 Dynamic Loudness Contour4.9.1Loudness Biquads 4.9.2Loudness Gain4.11 AllPass Function 4.10 Dynamic Range Compression/Expansion DRCETable 4−3. Main Control Register 2 Description 4.12 Main Control Register 1 01h4.13 Main Control Register 2 43h Table 4−2. Main Control Register 1 DescriptionPage 5.1.1Filter Coefficients Figure 5−1. Biquad Cascade Configuration5 Filter Processor 5.1 Biquad BlockPage Figure 6−1. Typical I 2C Data Transfer Sequence 6 I2C Serial Control Interface6.1 Introduction 6.2 I2C ProtocolTable 6−2. I 2C Address Byte Table 6.3 Operation6.3.1Write Cycle Example Table 6−1. I 2C Protocol Definitions6.3.3I2C Wait States 6.3.2TAS3002 I2C Readback ExampleTable 6−3. I 2C Wait States 6.4 SMBus Operation6.4.1Block Write Protocol 6.4.2Write Byte Protocol6.4.4TAS3002 SMBus Readback 6.4.3Wait StatesPage 7 Microcontroller Operation 7.2 Power-Up/Power-DownReset7.2.1Power-UpSequence 7.2.2ResetTAS3002 7.2.3Reset CircuitFigure 7−1. TAS3002 Reset Circuit 7.2.4Fast Load Mode7.2.5Codec Reset 7.3 Power-DownMode7.5 Internal Interface 7.3.1Power-DownTiming SequenceFigure 7−2. Power-DownTiming Sequence 7.4 Test ModeTable 7−1. GPI Terminal Programming 7.6.2GPI ArchitectureSlave Write GPI Power Down Figure 7−3. Internal Interface Flow ChartRestore Volume and MCR Start Power Up Initialize Default EEPROMTable 7−2. 512-ByteEEPROM Memory Map 2.0 Channels 7.7 External EEPROM Memory MapsTAS3002 ADDRESSBYTE NUMBER FUNCTIONCATEGORY TAS3002 ADDRESSNUMBER FUNCTIONCATEGORY TAS3002 ADDRESSNUMBER FUNCTION8.2 Recommended Operating Conditions 8 Electrical CharacteristicsStatic Digital Specifications 8.4 ADC Digital Filter Figure 8−1. ADC Digital Filter Characteristics8.5 Analog-to-DigitalConverter Figure 8−4. ADC High-PassFilter Characteristics8.7 DAC Interpolation Filter 8.6 Input Multiplexer8.9 DAC Output Performance Data 8.8 Digital-to-AnalogConverterFigure 8−7. I 2C Bus Timing 8.10 I2C Serial Port Timing CharacteristicsClock 9 System DiagramsFigure 9−1. Stereo Application TAS3002TAS3002 TAS3001Figure 9−2. TAS3002 Device, 2.1 Channels PLASTIC QUAD FLATPACK 10 Mechanical InformationPFB S-PQFP-G48 10−2