Texas Instruments TAS3002 manual Filter Processor, Biquad Block, 5.1.1Filter Coefficients

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5 Filter Processor

5.1 Biquad Block

The biquad block consists of seven digital biquad filters per channel organized in a cascade structure, as shown in Figure 5−1. Each of these biquad filters has five downloadable 24-bit (4.20) coefficients. Each stereo channel has independent coefficients.

Biquad 0

Biquad 1 ...

Biquad 6

Figure 5−1. Biquad Cascade Configuration

5.1.1Filter Coefficients

The filter coefficients for the TAS3002 device are downloaded through the I2C port and loaded into the biquad memory space. Each biquad filter memory space has an independent address. Digital audio data coming into the device is processed by the biquad block and then converted into analog waveforms by the DAC. Alternatively, filters can be loaded by asserting terminals on the GPI port.

5.1.2Biquad Structure

The biquad structure that is used for the parametric equalization filters is as follows:

b		0	) b	1	z*1 ) b	2	z*2
H(z) +
			) a z*1 ) a				z*2
a		0				2			(1)
				1
			NOTE: a0 is fixed at value 1 and is not downloadable.
The coefficients for these filters are represented in 4.20 format—4									bits for the integer part and 20 bits for the fractional

part. In order to transmit them over I2C, it is necessary to separate each coefficient into three bytes. The upper 4 bits of byte 2 comprise the integer part; the lower 4 bytes of byte 2 plus byte 1 and byte 0 comprise the fractional part.

The filters can be designed using the automatic loudspeaker equalization program (ALE) or a script running under MatLab named Filtermaker. Both of these tools are available from Texas Instruments.

5−1

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Contents 2001 Data ManualTAS3002 Digital Audio Processor With CodecIMPORTANT NOTICE 1.2Features 1 Introduction1.1 Description 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram Table 1−1. TAS3002 Terminal Functions 1.4 Terminal Assignments1.5 Terminal Functions Figure 1−2. TAS3002 Terminal AssignmentsTable 1−1. TAS3002 Terminal Functions Continued Page 2 Audio Data Formats 2.1 Serial Interface FormatsTable 2−1. Serial Interface Options … … … … … … … …2.2 Digital Output Modes … … … …… … … … 2.2.2I2S Serial-InterfaceFormatFigure 2−2. I 2S Serial-InterfaceFormat … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0 2.3 Switching CharacteristicsPARAMETER UNITPage 3.2.1Direct Analog Output 3 Analog Input/Output3.1 Analog Input 3.2 Analog Output3.2.2Analog Output With Gain Figure 3−2. VCOM Decoupling NetworkFigure 3−3. Analog Output With External Amplifier 3.2.3Reference Voltage Filter TAS3002Figure 3−4. TAS3002 Reference Voltage Filter Page 4.3 Input Mixer Control 4.1 Soft Volume Update4 Audio Control/Enhancement Functions 4.2 Software Soft Mute4.4 Mono Mixer Control 4.5 Treble ControlFigure 4−1. TAS3002 Mixer Function 4.6 Bass Control 4.7 De-EmphasisMode DMFigure 4−2. De-EmphasisMode Frequency Response Table 4−1. Analog Control Register Description 4.8 Analog Control Register 40h4.9.3Loudness Contour Operation 4.9 Dynamic Loudness Contour4.9.1Loudness Biquads 4.9.2Loudness Gain4.11 AllPass Function 4.10 Dynamic Range Compression/Expansion DRCETable 4−3. Main Control Register 2 Description 4.12 Main Control Register 1 01h4.13 Main Control Register 2 43h Table 4−2. Main Control Register 1 DescriptionPage 5.1.1Filter Coefficients Figure 5−1. Biquad Cascade Configuration5 Filter Processor 5.1 Biquad BlockPage Figure 6−1. Typical I 2C Data Transfer Sequence 6 I2C Serial Control Interface6.1 Introduction 6.2 I2C ProtocolTable 6−2. I 2C Address Byte Table 6.3 Operation6.3.1Write Cycle Example Table 6−1. I 2C Protocol Definitions6.3.3I2C Wait States 6.3.2TAS3002 I2C Readback ExampleTable 6−3. I 2C Wait States 6.4 SMBus Operation6.4.1Block Write Protocol 6.4.2Write Byte Protocol6.4.4TAS3002 SMBus Readback 6.4.3Wait StatesPage 7 Microcontroller Operation 7.2 Power-Up/Power-DownReset7.2.1Power-UpSequence 7.2.2ResetTAS3002 7.2.3Reset CircuitFigure 7−1. TAS3002 Reset Circuit 7.2.4Fast Load Mode7.2.5Codec Reset 7.3 Power-DownMode7.5 Internal Interface 7.3.1Power-DownTiming SequenceFigure 7−2. Power-DownTiming Sequence 7.4 Test ModeTable 7−1. GPI Terminal Programming 7.6.2GPI ArchitectureSlave Write GPI Power Down Figure 7−3. Internal Interface Flow ChartRestore Volume and MCR Start Power Up Initialize Default EEPROMTable 7−2. 512-ByteEEPROM Memory Map 2.0 Channels 7.7 External EEPROM Memory MapsTAS3002 ADDRESSBYTE NUMBER FUNCTIONCATEGORY TAS3002 ADDRESSNUMBER FUNCTIONCATEGORY TAS3002 ADDRESSNUMBER FUNCTION8 Electrical Characteristics Static Digital Specifications8.2 Recommended Operating Conditions 8.4 ADC Digital Filter Figure 8−1. ADC Digital Filter Characteristics8.5 Analog-to-DigitalConverter Figure 8−4. ADC High-PassFilter Characteristics8.7 DAC Interpolation Filter 8.6 Input Multiplexer8.9 DAC Output Performance Data 8.8 Digital-to-AnalogConverterFigure 8−7. I 2C Bus Timing 8.10 I2C Serial Port Timing CharacteristicsClock 9 System DiagramsFigure 9−1. Stereo Application TAS3002TAS3001 Figure 9−2. TAS3002 Device, 2.1 ChannelsTAS3002 10 Mechanical Information PFB S-PQFP-G48PLASTIC QUAD FLATPACK 10−2