Texas Instruments TAS3002 Microcontroller Operation, General Description, 7.2.1Power-UpSequence

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7 Microcontroller Operation

7 Microcontroller Operation

The TAS3002 device contains an internal microcontroller programmed by Texas Instruments to perform housekeeping and interface functions. Additionally, it handles I2C communication and general purpose input functions.

7.1 General Description

The microcontroller uses a 256fS system clock and can access up to 8K bytes of memory. It interfaces with the digital audio interface I2C master/slave for downloading data and coefficients. It also interfaces with two internal DSPs for transferring coefficients and other information.

The TAS3002 coefficients are loaded through I2C in the master or slave mode. Standard audio processing functions (volume, bass, and treble) can be controlled/activated through external switches connected to the six GPI terminals. Upon reset, the internal microcontroller sets all coefficients and audio parameters to the default values. See Section 7.2.2 for default values.

If the TAS3002 address is 68h (ADDR_SEL=0), it becomes the bus master device and attempts to load parameters and coefficients from the external EEPROM. If no EEPROM is present, the TAS3002 device remains in its default condition. If addresses other than 68h/69h are set, the TAS3002 device only operates as an I2C slave device.

If the microcontroller determines the TAS3002 device has an I2C address of 68h/69h and the EEPROM is present, the microcontroller downloads coefficients from the EEPROM. Once the download is complete, it enables the serial audio in the mode defined by an I2C write to the MCR to transfer data into and out of the device. Before reading the EEPROM, the serial audio port defaults to I2S mode.

The TAS3002 device allows the user to update volume, bass, and treble dynamically by an I2C slave command or by a simple GPI input. The GPI can select volume up and down, bass/treble up and down, or digital equalizations. Up to five different equalizations (that is, flat, jazz, rock, voice, etc.) can be stored in the external EEPROM. Also, DRCE, MCR1, MCR2, and loudness contour are enabled and disabled by I2C.

When the TAS3002 device operates in the I2C master mode, it echoes changes to all of its functions to other I2C addresses that are defined in its external EEPROM. If no addresses are defined, it does not echo.

7.2 Power-Up/Power-Down Reset

7.2.1Power-Up Sequence

An active low on terminal 6 (RESET) while MCLK is running resets the internal microcontroller and DSPs. RESET synchronizes internally and can be asserted asynchronously or with the simple RC circuit in Figure 7−1. On reset, SCL and SDA go to a high-impedance state. If the I2C address is set to 68h, approximately 400 ∝s after RESET returns to a 1, the device sends a one-byte query via I2C to look for an EEPROM. If an EEPROM is found, the TAS3002 becomes an I2C master; otherwise, it becomes an I2C slave. When using address 68h in the slave mode, an external master must wait until after the EEPROM query or else bus contention and improper operation occur.

I2C address x6Ah does not query the bus for an EEPROM. The address for the EEPROM is A0h.

7.2.2Reset

The TAS3002 device has an asynchronous reset terminal (RESET). This reset is synchronized with various clocks used in this device to generate a synchronous internal reset. Upon reset, the TAS3002 device goes through the following process:

•Clears all the RAM memory content

7−1

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Contents 2001 Data ManualTAS3002 Digital Audio Processor With CodecIMPORTANT NOTICE 1.1 Description 1.2Features1 Introduction 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram Table 1−1. TAS3002 Terminal Functions 1.4 Terminal Assignments1.5 Terminal Functions Figure 1−2. TAS3002 Terminal AssignmentsTable 1−1. TAS3002 Terminal Functions Continued Page Table 2−1. Serial Interface Options 2 Audio Data Formats2.1 Serial Interface Formats … … … … … … … …2.2 Digital Output Modes … … … …… … … … 2.2.2I2S Serial-InterfaceFormatFigure 2−2. I 2S Serial-InterfaceFormat … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0 2.3 Switching CharacteristicsPARAMETER UNITPage 3.2.1Direct Analog Output 3 Analog Input/Output3.1 Analog Input 3.2 Analog OutputFigure 3−3. Analog Output With External Amplifier 3.2.2Analog Output With GainFigure 3−2. VCOM Decoupling Network Figure 3−4. TAS3002 Reference Voltage Filter 3.2.3Reference Voltage FilterTAS3002 Page 4.3 Input Mixer Control 4.1 Soft Volume Update4 Audio Control/Enhancement Functions 4.2 Software Soft MuteFigure 4−1. TAS3002 Mixer Function 4.4 Mono Mixer Control4.5 Treble Control Figure 4−2. De-EmphasisMode Frequency Response 4.6 Bass Control4.7 De-EmphasisMode DM Table 4−1. Analog Control Register Description 4.8 Analog Control Register 40h4.9.3Loudness Contour Operation 4.9 Dynamic Loudness Contour4.9.1Loudness Biquads 4.9.2Loudness Gain4.11 AllPass Function 4.10 Dynamic Range Compression/Expansion DRCETable 4−3. Main Control Register 2 Description 4.12 Main Control Register 1 01h4.13 Main Control Register 2 43h Table 4−2. Main Control Register 1 DescriptionPage 5.1.1Filter Coefficients Figure 5−1. Biquad Cascade Configuration5 Filter Processor 5.1 Biquad BlockPage Figure 6−1. Typical I 2C Data Transfer Sequence 6 I2C Serial Control Interface6.1 Introduction 6.2 I2C ProtocolTable 6−2. I 2C Address Byte Table 6.3 Operation6.3.1Write Cycle Example Table 6−1. I 2C Protocol Definitions6.3.3I2C Wait States 6.3.2TAS3002 I2C Readback ExampleTable 6−3. I 2C Wait States 6.4 SMBus Operation6.4.1Block Write Protocol 6.4.2Write Byte Protocol6.4.4TAS3002 SMBus Readback 6.4.3Wait StatesPage 7 Microcontroller Operation 7.2 Power-Up/Power-DownReset7.2.1Power-UpSequence 7.2.2ResetTAS3002 7.2.3Reset CircuitFigure 7−1. TAS3002 Reset Circuit 7.2.4Fast Load Mode7.2.5Codec Reset 7.3 Power-DownMode7.5 Internal Interface 7.3.1Power-DownTiming SequenceFigure 7−2. Power-DownTiming Sequence 7.4 Test ModeTable 7−1. GPI Terminal Programming 7.6.2GPI ArchitectureSlave Write GPI Power Down Figure 7−3. Internal Interface Flow ChartRestore Volume and MCR Start Power Up Initialize Default EEPROMTable 7−2. 512-ByteEEPROM Memory Map 2.0 Channels 7.7 External EEPROM Memory MapsTAS3002 ADDRESSBYTE NUMBER FUNCTIONCATEGORY TAS3002 ADDRESSNUMBER FUNCTIONCATEGORY TAS3002 ADDRESSNUMBER FUNCTION8.2 Recommended Operating Conditions 8 Electrical CharacteristicsStatic Digital Specifications 8.4 ADC Digital Filter Figure 8−1. ADC Digital Filter Characteristics8.5 Analog-to-DigitalConverter Figure 8−4. ADC High-PassFilter Characteristics8.7 DAC Interpolation Filter 8.6 Input Multiplexer8.9 DAC Output Performance Data 8.8 Digital-to-AnalogConverterFigure 8−7. I 2C Bus Timing 8.10 I2C Serial Port Timing CharacteristicsClock 9 System DiagramsFigure 9−1. Stereo Application TAS3002TAS3002 TAS3001Figure 9−2. TAS3002 Device, 2.1 Channels PLASTIC QUAD FLATPACK 10 Mechanical InformationPFB S-PQFP-G48 10−2
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