Texas Instruments TAS3002 Analog Control Register 40h, 1. Analog Control Register Description

Contents Digital Audio Processor With Codec Data ManualTAS3002 2001IMPORTANT NOTICE 1 Introduction 1.2Features1.1 Description 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram Figure 1−2. TAS3002 Terminal Assignments 1.4 Terminal Assignments1.5 Terminal Functions Table 1−1. TAS3002 Terminal FunctionsTable 1−1. TAS3002 Terminal Functions Continued Page 2.1 Serial Interface Formats 2 Audio Data FormatsTable 2−1. Serial Interface Options … … … … … … … …2.2 Digital Output Modes … … … …… … … … 2.2.2I2S Serial-InterfaceFormatFigure 2−2. I 2S Serial-InterfaceFormat … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …UNIT 2.3 Switching CharacteristicsPARAMETER tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0Page 3.2 Analog Output 3 Analog Input/Output3.1 Analog Input 3.2.1Direct Analog OutputFigure 3−2. VCOM Decoupling Network 3.2.2Analog Output With GainFigure 3−3. Analog Output With External Amplifier TAS3002 3.2.3Reference Voltage FilterFigure 3−4. TAS3002 Reference Voltage Filter Page 4.2 Software Soft Mute 4.1 Soft Volume Update4 Audio Control/Enhancement Functions 4.3 Input Mixer Control4.5 Treble Control 4.4 Mono Mixer ControlFigure 4−1. TAS3002 Mixer Function 4.7 De-EmphasisMode DM 4.6 Bass ControlFigure 4−2. De-EmphasisMode Frequency Response 4.8 Analog Control Register 40h Table 4−1. Analog Control Register Description4.9.2Loudness Gain 4.9 Dynamic Loudness Contour4.9.1Loudness Biquads 4.9.3Loudness Contour Operation4.10 Dynamic Range Compression/Expansion DRCE 4.11 AllPass FunctionTable 4−2. Main Control Register 1 Description 4.12 Main Control Register 1 01h4.13 Main Control Register 2 43h Table 4−3. Main Control Register 2 DescriptionPage 5.1 Biquad Block Figure 5−1. Biquad Cascade Configuration5 Filter Processor 5.1.1Filter CoefficientsPage 6.2 I2C Protocol 6 I2C Serial Control Interface6.1 Introduction Figure 6−1. Typical I 2C Data Transfer SequenceTable 6−1. I 2C Protocol Definitions 6.3 Operation6.3.1Write Cycle Example Table 6−2. I 2C Address Byte Table6.3.2TAS3002 I2C Readback Example 6.3.3I2C Wait States6.4.2Write Byte Protocol 6.4 SMBus Operation6.4.1Block Write Protocol Table 6−3. I 2C Wait States6.4.3Wait States 6.4.4TAS3002 SMBus ReadbackPage 7.2.2Reset 7.2 Power-Up/Power-DownReset7.2.1Power-UpSequence 7 Microcontroller Operation7.2.4Fast Load Mode 7.2.3Reset CircuitFigure 7−1. TAS3002 Reset Circuit TAS30027.3 Power-DownMode 7.2.5Codec Reset7.4 Test Mode 7.3.1Power-DownTiming SequenceFigure 7−2. Power-DownTiming Sequence 7.5 Internal Interface7.6.2GPI Architecture Table 7−1. GPI Terminal ProgrammingStart Power Up Initialize Default EEPROM Figure 7−3. Internal Interface Flow ChartRestore Volume and MCR Slave Write GPI Power Down7.7 External EEPROM Memory Maps Table 7−2. 512-ByteEEPROM Memory Map 2.0 ChannelsFUNCTION ADDRESSBYTE NUMBER TAS3002FUNCTION TAS3002 ADDRESSNUMBER CATEGORYFUNCTION TAS3002 ADDRESSNUMBER CATEGORYStatic Digital Specifications 8 Electrical Characteristics8.2 Recommended Operating Conditions Figure 8−1. ADC Digital Filter Characteristics 8.4 ADC Digital FilterFigure 8−4. ADC High-PassFilter Characteristics 8.5 Analog-to-DigitalConverter8.6 Input Multiplexer 8.7 DAC Interpolation Filter8.8 Digital-to-AnalogConverter 8.9 DAC Output Performance Data8.10 I2C Serial Port Timing Characteristics Figure 8−7. I 2C Bus TimingTAS3002 9 System DiagramsFigure 9−1. Stereo Application ClockFigure 9−2. TAS3002 Device, 2.1 Channels TAS3001TAS3002 PFB S-PQFP-G48 10 Mechanical InformationPLASTIC QUAD FLATPACK 10−2