Texas Instruments manual 1. TAS3002 Terminal Functions Continued

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							Table 1−1. TAS3002 Terminal Functions (Continued)

			TERMINAL			I/O				DESCRIPTION
	NAME				NO.	I/O				DESCRIPTION
	NAME				NO.

	CAP_PLL				10	I	Loop filter for internal phase-locked loop (PLL)

	CLKSEL				11	I	Logic low selects 256 fS; logic high selects 512 fS MCLK
	CS1				7	I	I2C address bit A0; low = 68h, high = 6Ah
	DVDD				17	I	Digital power supply (3.3 V)
	DVSS				18	I	Digital ground
	GPI0				28	I	Switch input terminals
	GPI1				29
	GPI2				30
	GPI3				31
	GPI4				32
	GPI5				33

					21	I	Digital audio I/O control (low = input; high = output)
	IFM/S				21	I	Digital audio I/O control (low = input; high = output)

					5	O	Low when analog input A is selected (will sink 4 mA)
	INPA				5	O	Low when analog input A is selected (will sink 4 mA)

	LINA				1	I	Left channel analog input 1

	LINB				48	I	Left channel analog input 2

	LRCLK/O				19	I/O	Left/right clock input/output (output when				is high)
	LRCLK/O				19	I/O	Left/right clock input/output (output when			IFM/S	is high)
	MCLKO				12	O	MCLK output for slave devices

	NC				34		No connection; Can be used as a printed circuit board routing channel

	NC				36		No connection; Can be used as a printed circuit board routing channel

	PWR_DN				8	I	Logic high places the TAS3002 device in power-down mode

					6	I	Logic low resets the TAS3002 device to the initial state
	RESET				6	I	Logic low resets the TAS3002 device to the initial state

	RINA				40	I	Right channel analog input 1

	RINB				41	I	Right channel analog input 2

	SCL				15	I/O	I2C clock connection
	SCLK/O				20	I/O	Shift (bit) clock input (output when		is high)
	SCLK/O				20	I/O	Shift (bit) clock input (output when	IFM/S	is high)
	SDA				16	I/O	I2C data connection
	SDIN1				22	I	Serial data input 1

	SDIN2				23	I	Serial data input 2

	SDOUT0				25	O	Serial data output from ADC

	SDOUT1				26	O	Serial data output (from internal audio processing)

	SDOUT2				24	O	Serial data output (a monaural mix of left and right, before processing)

	TEST				9	I	Reserved manufacturing test terminal; connect to DVSS
	VCOM				38	O	Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-∝F and 0.1-∝F
							capacitors)

	VREFM				45	I	ADC minus voltage reference
	VREFP				44	I	ADC plus voltage reference
	VRFILT				2	O	Voltage reference low pass filter
	XTALI/MCLK				13	I	Crystal or external MCLK input

	XTALO				14	I	Crystal input (crystal is connected between terminals 13 and 14)

1−5

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Contents 2001 Data ManualTAS3002 Digital Audio Processor With CodecIMPORTANT NOTICE 1 Introduction 1.2Features1.1 Description 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram Table 1−1. TAS3002 Terminal Functions 1.4 Terminal Assignments1.5 Terminal Functions Figure 1−2. TAS3002 Terminal AssignmentsTable 1−1. TAS3002 Terminal Functions Continued Page 2.1 Serial Interface Formats 2 Audio Data FormatsTable 2−1. Serial Interface Options … … … … … … … …2.2 Digital Output Modes … … … …… … … … 2.2.2I2S Serial-InterfaceFormatFigure 2−2. I 2S Serial-InterfaceFormat … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0 2.3 Switching CharacteristicsPARAMETER UNITPage 3.2.1Direct Analog Output 3 Analog Input/Output3.1 Analog Input 3.2 Analog OutputFigure 3−2. VCOM Decoupling Network 3.2.2Analog Output With GainFigure 3−3. Analog Output With External Amplifier TAS3002 3.2.3Reference Voltage FilterFigure 3−4. TAS3002 Reference Voltage Filter Page 4.3 Input Mixer Control 4.1 Soft Volume Update4 Audio Control/Enhancement Functions 4.2 Software Soft Mute4.5 Treble Control 4.4 Mono Mixer ControlFigure 4−1. TAS3002 Mixer Function 4.7 De-EmphasisMode DM 4.6 Bass ControlFigure 4−2. De-EmphasisMode Frequency Response Table 4−1. Analog Control Register Description 4.8 Analog Control Register 40h4.9.3Loudness Contour Operation 4.9 Dynamic Loudness Contour4.9.1Loudness Biquads 4.9.2Loudness Gain4.11 AllPass Function 4.10 Dynamic Range Compression/Expansion DRCETable 4−3. Main Control Register 2 Description 4.12 Main Control Register 1 01h4.13 Main Control Register 2 43h Table 4−2. Main Control Register 1 DescriptionPage 5.1.1Filter Coefficients Figure 5−1. Biquad Cascade Configuration5 Filter Processor 5.1 Biquad BlockPage Figure 6−1. Typical I 2C Data Transfer Sequence 6 I2C Serial Control Interface6.1 Introduction 6.2 I2C ProtocolTable 6−2. I 2C Address Byte Table 6.3 Operation6.3.1Write Cycle Example Table 6−1. I 2C Protocol Definitions6.3.3I2C Wait States 6.3.2TAS3002 I2C Readback ExampleTable 6−3. I 2C Wait States 6.4 SMBus Operation6.4.1Block Write Protocol 6.4.2Write Byte Protocol6.4.4TAS3002 SMBus Readback 6.4.3Wait StatesPage 7 Microcontroller Operation 7.2 Power-Up/Power-DownReset7.2.1Power-UpSequence 7.2.2ResetTAS3002 7.2.3Reset CircuitFigure 7−1. TAS3002 Reset Circuit 7.2.4Fast Load Mode7.2.5Codec Reset 7.3 Power-DownMode7.5 Internal Interface 7.3.1Power-DownTiming SequenceFigure 7−2. Power-DownTiming Sequence 7.4 Test ModeTable 7−1. GPI Terminal Programming 7.6.2GPI ArchitectureSlave Write GPI Power Down Figure 7−3. Internal Interface Flow ChartRestore Volume and MCR Start Power Up Initialize Default EEPROMTable 7−2. 512-ByteEEPROM Memory Map 2.0 Channels 7.7 External EEPROM Memory MapsTAS3002 ADDRESSBYTE NUMBER FUNCTIONCATEGORY TAS3002 ADDRESSNUMBER FUNCTIONCATEGORY TAS3002 ADDRESSNUMBER FUNCTIONStatic Digital Specifications 8 Electrical Characteristics8.2 Recommended Operating Conditions 8.4 ADC Digital Filter Figure 8−1. ADC Digital Filter Characteristics8.5 Analog-to-DigitalConverter Figure 8−4. ADC High-PassFilter Characteristics8.7 DAC Interpolation Filter 8.6 Input Multiplexer8.9 DAC Output Performance Data 8.8 Digital-to-AnalogConverterFigure 8−7. I 2C Bus Timing 8.10 I2C Serial Port Timing CharacteristicsClock 9 System DiagramsFigure 9−1. Stereo Application TAS3002Figure 9−2. TAS3002 Device, 2.1 Channels TAS3001TAS3002 PFB S-PQFP-G48 10 Mechanical InformationPLASTIC QUAD FLATPACK 10−2