Texas Instruments TAS3002 manual Audio Data Formats, Serial Interface Formats

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2 Audio Data Formats

2 Audio Data Formats

2.1 Serial Interface Formats

The TAS3002 device works in master or slave mode.

In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be connected to XTALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and 20 (SCLK/O) becoming outputs to drive slave devices.

In the slave mode, IFM/S is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options for selecting the clock rates. If the 512fS MCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate of 512fS must be supplied. If the 256fS MCLK is selected, CLKSEL is tied low and an MCLK of 256fS must be supplied. In both cases, an LRCLK of 64SCLK must be supplied.

•MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.

•If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I2S, right justified, and left justified. Table 2−1 indicates how the 13 options are selected using the I 2C bus and the main control register (MCR, I2C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64fS. Additionally, the 16-bit mode operates at 32fS.

Table 2−1. Serial Interface Options

MODE

MCR BIT (6)

MCR BIT (5−4)

MCR BIT (1−0)

SERIAL INTERFACE

SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0

 

 

 

 

 

 

 

 

 

0

0

00

00

16-bit, 32 fS

1

1

00

00

16-bit, left justified, 64 fS

2

1

01

00

16-bit, right justified, 64 fS

3

1

10

00

16-bit, I2S, 64 f

 

 

 

 

S

4

1

00

01

18-bit, left justified, 64 fS

5

1

01

01

18-bit, right justified, 64 fS

6

1

10

01

18-bit, I2S, 64 fS

7

1

00

10

20-bit, left justified, 64 fS

8

1

01

10

20-bit, right justified, 64 fS

9

1

10

10

20-bit, I2S, 64 fS

10

1

00

11

24-bit, left justified, 64 fS

11

1

01

11

24-bit, right justified, 64 fS

12

1

10

11

24-bit, I2S, 64 fS

Figure 2−1 through Figure 2−3 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the different interface protocols.

2−1

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Contents TAS3002 Data ManualDigital Audio Processor With Codec 2001IMPORTANT NOTICE 1.2Features 1 Introduction1.1 Description 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram 1.5 Terminal Functions 1.4 Terminal AssignmentsFigure 1−2. TAS3002 Terminal Assignments Table 1−1. TAS3002 Terminal FunctionsTable 1−1. TAS3002 Terminal Functions Continued Page 2 Audio Data Formats 2.1 Serial Interface FormatsTable 2−1. Serial Interface Options 2.2 Digital Output Modes … … … …… … … … … … … …Figure 2−2. I 2S Serial-InterfaceFormat 2.2.2I2S Serial-InterfaceFormat… … … … … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …PARAMETER 2.3 Switching CharacteristicsUNIT tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0Page 3.1 Analog Input 3 Analog Input/Output3.2 Analog Output 3.2.1Direct Analog Output3.2.2Analog Output With Gain Figure 3−2. VCOM Decoupling NetworkFigure 3−3. Analog Output With External Amplifier 3.2.3Reference Voltage Filter TAS3002Figure 3−4. TAS3002 Reference Voltage Filter Page 4 Audio Control/Enhancement Functions 4.1 Soft Volume Update4.2 Software Soft Mute 4.3 Input Mixer Control4.4 Mono Mixer Control 4.5 Treble ControlFigure 4−1. TAS3002 Mixer Function 4.6 Bass Control 4.7 De-EmphasisMode DMFigure 4−2. De-EmphasisMode Frequency Response Table 4−1. Analog Control Register Description 4.8 Analog Control Register 40h4.9.1Loudness Biquads 4.9 Dynamic Loudness Contour4.9.2Loudness Gain 4.9.3Loudness Contour Operation4.11 AllPass Function 4.10 Dynamic Range Compression/Expansion DRCE4.13 Main Control Register 2 43h 4.12 Main Control Register 1 01hTable 4−2. Main Control Register 1 Description Table 4−3. Main Control Register 2 DescriptionPage 5 Filter Processor Figure 5−1. Biquad Cascade Configuration5.1 Biquad Block 5.1.1Filter CoefficientsPage 6.1 Introduction 6 I2C Serial Control Interface6.2 I2C Protocol Figure 6−1. Typical I 2C Data Transfer Sequence6.3.1Write Cycle Example 6.3 OperationTable 6−1. I 2C Protocol Definitions Table 6−2. I 2C Address Byte Table6.3.3I2C Wait States 6.3.2TAS3002 I2C Readback Example6.4.1Block Write Protocol 6.4 SMBus Operation6.4.2Write Byte Protocol Table 6−3. I 2C Wait States6.4.4TAS3002 SMBus Readback 6.4.3Wait StatesPage 7.2.1Power-UpSequence 7.2 Power-Up/Power-DownReset7.2.2Reset 7 Microcontroller OperationFigure 7−1. TAS3002 Reset Circuit 7.2.3Reset Circuit7.2.4Fast Load Mode TAS30027.2.5Codec Reset 7.3 Power-DownModeFigure 7−2. Power-DownTiming Sequence 7.3.1Power-DownTiming Sequence7.4 Test Mode 7.5 Internal InterfaceTable 7−1. GPI Terminal Programming 7.6.2GPI ArchitectureRestore Volume and MCR Figure 7−3. Internal Interface Flow ChartStart Power Up Initialize Default EEPROM Slave Write GPI Power DownTable 7−2. 512-ByteEEPROM Memory Map 2.0 Channels 7.7 External EEPROM Memory MapsBYTE NUMBER ADDRESSFUNCTION TAS3002NUMBER TAS3002 ADDRESSFUNCTION CATEGORYNUMBER TAS3002 ADDRESSFUNCTION CATEGORY8 Electrical Characteristics Static Digital Specifications8.2 Recommended Operating Conditions 8.4 ADC Digital Filter Figure 8−1. ADC Digital Filter Characteristics8.5 Analog-to-DigitalConverter Figure 8−4. ADC High-PassFilter Characteristics8.7 DAC Interpolation Filter 8.6 Input Multiplexer8.9 DAC Output Performance Data 8.8 Digital-to-AnalogConverterFigure 8−7. I 2C Bus Timing 8.10 I2C Serial Port Timing CharacteristicsFigure 9−1. Stereo Application 9 System DiagramsTAS3002 ClockTAS3001 Figure 9−2. TAS3002 Device, 2.1 ChannelsTAS3002 10 Mechanical Information PFB S-PQFP-G48PLASTIC QUAD FLATPACK 10−2
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