Texas Instruments TAS3002 External EEPROM Memory Maps, 2. 512-ByteEEPROM Memory Map 2.0 Channels

Page 41

7.7 External EEPROM Memory Maps

Table 7−2 through Table 7−5 show the 512-byte and 2048-byte EEPROM memory maps.

Table 7−2. 512-Byte EEPROM Memory Map 2.0 Channels

ADDRESS

BYTE NUMBER

 

FUNCTION

 

 

 

 

 

000h

1

Signature (2Ah)

 

 

 

 

 

 

 

001h

1

ID byte = 0000 0000

 

 

 

 

 

 

 

002h

1

MCR

 

 

 

 

 

 

 

003h−00Bh

9

Mixer left gain

 

 

 

 

 

 

 

00Ch−014h

9

Mixer right gain

 

 

 

 

 

 

015h−01Ah

2

DRC (ratio, threshold, energyα, attackα, decayα)

 

 

 

 

 

01Bh

1

Bass

 

 

 

 

 

 

 

01Ch

1

Treble

 

 

 

 

 

 

 

01Dh−022h

6

Volume

 

 

 

 

 

 

 

031h−03Fh

15

Biquad 0

 

 

 

 

 

 

 

040h−04Eh

15

Biquad 1

 

 

 

 

 

 

 

04Fh−05Dh

15

Biquad 2

 

 

 

 

 

 

 

05Eh−06Ch

15

Biquad 3

 

Left channel

06Dh−07Bh

15

Biquad 4

 

 

 

 

 

 

 

07Ch−08Ah

15

Biquad 5

 

 

 

 

 

 

 

08Bh−099h

15

Biquad 6

 

 

 

 

 

 

 

09Ah

1

0 dB/bass

 

 

 

 

 

 

 

09Bh

1

0 dB/treble

 

 

 

 

 

 

 

09Ch−0A1h

6

Bass break

 

 

 

 

 

 

 

0A2h−0A7h

6

Treble break

 

 

 

 

 

 

 

0A8h−110h

105

Bass delta

 

 

 

 

 

 

 

111h−179h

105

Treble delta

 

 

 

 

 

 

 

17Ah−17Fh

6

Bass set point

 

 

 

 

 

 

 

180h−185h

6

Treble set point

 

 

 

 

 

 

 

186h−194h

15

Biquad 0

 

 

 

 

 

 

 

195h−1A3h

15

Biquad 1

 

 

 

 

 

 

 

1A4h−1B2h

15

Biquad 2

 

 

 

 

 

 

 

1B3h−1C1h

15

Biquad 3

 

Right channel

1C2h−1D0h

15

Biquad 4

 

 

 

 

 

 

 

1D1h−1DFh

15

Biquad 5

 

 

 

 

 

 

 

1E0h−1EEh

15

Biquad 6

 

 

 

 

 

 

 

NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.

7−7

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Contents TAS3002 Data ManualDigital Audio Processor With Codec 2001IMPORTANT NOTICE 1.1 Description 1.2Features1 Introduction 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram 1.5 Terminal Functions 1.4 Terminal AssignmentsFigure 1−2. TAS3002 Terminal Assignments Table 1−1. TAS3002 Terminal FunctionsTable 1−1. TAS3002 Terminal Functions Continued Page Table 2−1. Serial Interface Options 2 Audio Data Formats2.1 Serial Interface Formats 2.2 Digital Output Modes … … … …… … … … … … … …Figure 2−2. I 2S Serial-InterfaceFormat 2.2.2I2S Serial-InterfaceFormat… … … … … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …PARAMETER 2.3 Switching CharacteristicsUNIT tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0Page 3.1 Analog Input 3 Analog Input/Output3.2 Analog Output 3.2.1Direct Analog OutputFigure 3−3. Analog Output With External Amplifier 3.2.2Analog Output With GainFigure 3−2. VCOM Decoupling Network Figure 3−4. TAS3002 Reference Voltage Filter 3.2.3Reference Voltage FilterTAS3002 Page 4 Audio Control/Enhancement Functions 4.1 Soft Volume Update4.2 Software Soft Mute 4.3 Input Mixer ControlFigure 4−1. TAS3002 Mixer Function 4.4 Mono Mixer Control4.5 Treble Control Figure 4−2. De-EmphasisMode Frequency Response 4.6 Bass Control4.7 De-EmphasisMode DM Table 4−1. Analog Control Register Description 4.8 Analog Control Register 40h4.9.1Loudness Biquads 4.9 Dynamic Loudness Contour4.9.2Loudness Gain 4.9.3Loudness Contour Operation4.11 AllPass Function 4.10 Dynamic Range Compression/Expansion DRCE4.13 Main Control Register 2 43h 4.12 Main Control Register 1 01hTable 4−2. Main Control Register 1 Description Table 4−3. Main Control Register 2 DescriptionPage 5 Filter Processor Figure 5−1. Biquad Cascade Configuration5.1 Biquad Block 5.1.1Filter CoefficientsPage 6.1 Introduction 6 I2C Serial Control Interface6.2 I2C Protocol Figure 6−1. Typical I 2C Data Transfer Sequence6.3.1Write Cycle Example 6.3 OperationTable 6−1. I 2C Protocol Definitions Table 6−2. I 2C Address Byte Table6.3.3I2C Wait States 6.3.2TAS3002 I2C Readback Example6.4.1Block Write Protocol 6.4 SMBus Operation6.4.2Write Byte Protocol Table 6−3. I 2C Wait States6.4.4TAS3002 SMBus Readback 6.4.3Wait StatesPage 7.2.1Power-UpSequence 7.2 Power-Up/Power-DownReset7.2.2Reset 7 Microcontroller OperationFigure 7−1. TAS3002 Reset Circuit 7.2.3Reset Circuit7.2.4Fast Load Mode TAS30027.2.5Codec Reset 7.3 Power-DownModeFigure 7−2. Power-DownTiming Sequence 7.3.1Power-DownTiming Sequence7.4 Test Mode 7.5 Internal InterfaceTable 7−1. GPI Terminal Programming 7.6.2GPI ArchitectureRestore Volume and MCR Figure 7−3. Internal Interface Flow ChartStart Power Up Initialize Default EEPROM Slave Write GPI Power DownTable 7−2. 512-ByteEEPROM Memory Map 2.0 Channels 7.7 External EEPROM Memory MapsBYTE NUMBER ADDRESSFUNCTION TAS3002NUMBER TAS3002 ADDRESSFUNCTION CATEGORYNUMBER TAS3002 ADDRESSFUNCTION CATEGORY8.2 Recommended Operating Conditions 8 Electrical CharacteristicsStatic Digital Specifications 8.4 ADC Digital Filter Figure 8−1. ADC Digital Filter Characteristics8.5 Analog-to-DigitalConverter Figure 8−4. ADC High-PassFilter Characteristics8.7 DAC Interpolation Filter 8.6 Input Multiplexer8.9 DAC Output Performance Data 8.8 Digital-to-AnalogConverterFigure 8−7. I 2C Bus Timing 8.10 I2C Serial Port Timing CharacteristicsFigure 9−1. Stereo Application 9 System DiagramsTAS3002 ClockTAS3002 TAS3001Figure 9−2. TAS3002 Device, 2.1 Channels PLASTIC QUAD FLATPACK 10 Mechanical InformationPFB S-PQFP-G48 10−2
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