Texas Instruments TAS3002 manual Main Control Register 1 01h, Main Control Register 2 43h

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4.12 Main Control Register 1 (01h)

The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2 (MCR2). The MCR1 register contains the bits associated with load speed, SCLK frequency, serial-port mode, and serial-port word length. It is accessed via I2C with the address 01h.

MCR1 (01h)

Bit	b7	b6	b5	b4	b3	b2	b1	b0

Type	R/W	R/W	R/W	R/W	R	R	R/W	R/W

Default	1	X	X	X	X	X	X	X

Table 4−2. Main Control Register 1 Description

BIT	FIELD NAME	TYPE			DESCRIPTION

7	FL	R/W	Fast load
			0	= Normal operation mode
			1	= Fast -load mode (default)

6	SC	R/W	SCLK frequency
			0	= SCLK is 32 fS.
			1	= SCLK is 64 fS.
5−4	E	R/W	Serial port mode
			00		= Left justified
			01		= Right justified
			10		= I2S
			11 = Reserved

3−2	Reserved	R	Reserved

1−0	W	R/W	Serial port word length
			00		= 16-bit
			01		= 18-bit
			10		= 20-bit
			11 = 24-bit

4.13 Main Control Register 2 (43h)

The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2 (MCR2). The MCR2 register contains the bits associated with the AllPass function and the download of bass and treble control information, and it is accessed via I2C with the address 43h.

MCR2 (43h)

Bit	7	6	5	4	3	2	1	0

Type	R/W	R	R	R	R	R	R/W	R

Default	0	0	0	x	x	x	0	0

Table 4−3. Main Control Register 2 Description

BIT	FIELD NAME	TYPE		DESCRIPTION

7	Reserved	R/W	0	= Normal operation (initial condition after reset)
			1	= Download bass and treble

6−5	Reserved	R	Reserved. Bits 6 and 5 return 0s when read.

4−2	Reserved	R	Undefined.

1	DM(1−0)	R/W	0	= Normal operation (initial condition after reset)
			1	= AllPass mode (bass and treble are still functional)

0	INP	R	Reserved. Bit 0 returns 0 when read.

4−7

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Contents TAS3002 Data ManualDigital Audio Processor With Codec 2001IMPORTANT NOTICE 1 Introduction 1.2Features1.1 Description 1.3Functional Block Diagram Figure 1−1. TAS3002 Block Diagram 1.5 Terminal Functions 1.4 Terminal AssignmentsFigure 1−2. TAS3002 Terminal Assignments Table 1−1. TAS3002 Terminal FunctionsTable 1−1. TAS3002 Terminal Functions Continued Page 2.1 Serial Interface Formats 2 Audio Data FormatsTable 2−1. Serial Interface Options 2.2 Digital Output Modes … … … …… … … … … … … …Figure 2−2. I 2S Serial-InterfaceFormat 2.2.2I2S Serial-InterfaceFormat… … … … … … … …… … … … 2.2.3MSB-Left-Justified, Serial-InterfaceFormat… … … … … … … …PARAMETER 2.3 Switching CharacteristicsUNIT tcSCLK SCLK LRCLK tdSDOUT SDOUT1 SDOUT2 SDOUT0Page 3.1 Analog Input 3 Analog Input/Output3.2 Analog Output 3.2.1Direct Analog OutputFigure 3−2. VCOM Decoupling Network 3.2.2Analog Output With GainFigure 3−3. Analog Output With External Amplifier TAS3002 3.2.3Reference Voltage FilterFigure 3−4. TAS3002 Reference Voltage Filter Page 4 Audio Control/Enhancement Functions 4.1 Soft Volume Update4.2 Software Soft Mute 4.3 Input Mixer Control4.5 Treble Control 4.4 Mono Mixer ControlFigure 4−1. TAS3002 Mixer Function 4.7 De-EmphasisMode DM 4.6 Bass ControlFigure 4−2. De-EmphasisMode Frequency Response Table 4−1. Analog Control Register Description 4.8 Analog Control Register 40h4.9.1Loudness Biquads 4.9 Dynamic Loudness Contour4.9.2Loudness Gain 4.9.3Loudness Contour Operation4.11 AllPass Function 4.10 Dynamic Range Compression/Expansion DRCE4.13 Main Control Register 2 43h 4.12 Main Control Register 1 01hTable 4−2. Main Control Register 1 Description Table 4−3. Main Control Register 2 DescriptionPage 5 Filter Processor Figure 5−1. Biquad Cascade Configuration5.1 Biquad Block 5.1.1Filter CoefficientsPage 6.1 Introduction 6 I2C Serial Control Interface6.2 I2C Protocol Figure 6−1. Typical I 2C Data Transfer Sequence6.3.1Write Cycle Example 6.3 OperationTable 6−1. I 2C Protocol Definitions Table 6−2. I 2C Address Byte Table6.3.3I2C Wait States 6.3.2TAS3002 I2C Readback Example6.4.1Block Write Protocol 6.4 SMBus Operation6.4.2Write Byte Protocol Table 6−3. I 2C Wait States6.4.4TAS3002 SMBus Readback 6.4.3Wait StatesPage 7.2.1Power-UpSequence 7.2 Power-Up/Power-DownReset7.2.2Reset 7 Microcontroller OperationFigure 7−1. TAS3002 Reset Circuit 7.2.3Reset Circuit7.2.4Fast Load Mode TAS30027.2.5Codec Reset 7.3 Power-DownModeFigure 7−2. Power-DownTiming Sequence 7.3.1Power-DownTiming Sequence7.4 Test Mode 7.5 Internal InterfaceTable 7−1. GPI Terminal Programming 7.6.2GPI ArchitectureRestore Volume and MCR Figure 7−3. Internal Interface Flow ChartStart Power Up Initialize Default EEPROM Slave Write GPI Power DownTable 7−2. 512-ByteEEPROM Memory Map 2.0 Channels 7.7 External EEPROM Memory MapsBYTE NUMBER ADDRESSFUNCTION TAS3002NUMBER TAS3002 ADDRESSFUNCTION CATEGORYNUMBER TAS3002 ADDRESSFUNCTION CATEGORYStatic Digital Specifications 8 Electrical Characteristics8.2 Recommended Operating Conditions 8.4 ADC Digital Filter Figure 8−1. ADC Digital Filter Characteristics8.5 Analog-to-DigitalConverter Figure 8−4. ADC High-PassFilter Characteristics8.7 DAC Interpolation Filter 8.6 Input Multiplexer8.9 DAC Output Performance Data 8.8 Digital-to-AnalogConverterFigure 8−7. I 2C Bus Timing 8.10 I2C Serial Port Timing CharacteristicsFigure 9−1. Stereo Application 9 System DiagramsTAS3002 ClockFigure 9−2. TAS3002 Device, 2.1 Channels TAS3001TAS3002 PFB S-PQFP-G48 10 Mechanical InformationPLASTIC QUAD FLATPACK 10−2