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When we buy new device such as Philips S1D13505 we often through away most of the documentation but the warranty. Very often issues with Philips S1D13505 begin only after the warranty period ends and you may want to find how to repair it or just do some service work. Even oftener it is hard to remember what does each function in Computer Monitor Philips S1D13505 is responsible for and what options to choose for expected result. Fortunately you can find all manuals for Computer Monitor on our side using links below.

Philips S1D13505 Technical Manual

Philips S1D13505 Technical Manual

556 pages4.87 Mb

3Customer Support Information
- Comprehensive Support Tools
- Evaluation / Demonstration Board
- Chip Documentation
  - Technical manual includes Data Sheet, Application Notes, and Programmers Reference.
- Software
- Application Engineering Support
  - Engineering and Sales Support is provided by:
5GRAPHICS S1D13505
- S1D13505 EMBEDDED RAMDAC LCD/CRT CONTROLLER October 2001
  - X23A-C-002-15 2
6GRAPHICS S1D13505
- - S1D13505
  - CPU
  - Driver
- 171.1 Scope
- 1.2 Overview Description
- 182 Features
  - 2.1 Memory Interface
  - 2.2 CPU Interface
  - 192.3 Display Support
  - 2.4 Display Modes
  - 2.5 Display Features
  - 2.6 Clock Source
  - 202.7 Miscellaneous
    - Epson Research and Development Page 15
- 213 Typical System Implementation Diagrams
  - Figure 3-1: Typical System Diagram (SH-4 Bus)
  - .
    - Figure 3-2: Typical System Diagram (SH-3 Bus)
      - SH-4
      - SH-3
      - Page 16 Epson Research and Development
    - 22Figure 3-3: Typical System Diagram (MC68K Bus 1, 16-Bit 68000)
    - Figure 3-4: Typical System Diagram (MC68K Bus 2, 32-Bit 68030)
      - MC68000
      - MC68030
      - Epson Research and Development Page 17
      - Issue Date: 01/02/02 X23A-A-001-14
    - 23Figure 3-5: Typical System Diagram (Generic Bus)
    - Figure 3-6: Typical System Diagram (NEC VR41xx (MIPS) Bus)
      - Generic
      - MIPS
      - Page 18 Epson Research and Development
    - 24Figure 3-7: Typical System Diagram (Philips PR31500/PR3 1700 Bus)
    - Figure 3-8: Typical System Diagram (Toshiba TX3912 Bu s)
      - PR31500 BUS
      - /PR31700
      - Philips
      - Toshiba TX3912
      - Epson Research and Development Page 19
    - 25Figure 3-9: Typical System Diagram (Power PC Bus)
    - Figure 3-10: Typical System Diagram (PC Card (PCMCIA) Bus)
      - PowerPC
      - 256Kx16
      - PC Card
- 264 Internal Description
  - 4.1 Block Diagram Showing Datapaths
  - 4.2 Block Descriptions 4.2.1 Register
  - 4.2.2 Host Interface
  - 4.2.3 CPU R/W
    - Page 22 Epson Research and Development
- 5 Pins
  - 5.1 Pinout Diagram
    - Figure 5-1: Pinout Diagram
    - 128-pin QFP15 surface mount package
- 28S1D13505
  - 295.2 Pin Description
    - Key:
  - 5.2.1 Host Interface
  - 355.2.2 Memory Interface
  - 375.2.3 LCD Interface
  - 5.2.4 CRT Interface
    - Table 5-2: LCD
  - 385.2.5 Miscellaneous
  - 395.3 Summary of Configuration Options
  - 405.4 Multiple Function Pin Mapping
    - Epson Research and Development Page 37
43}
- 5.5 CRT Interface
  - The following figure shows the external circuitry for the CRT interface.
    - Figure 5-3: External Circuitry for CRT Interface
      - 4.6 mA
  - OR
    - IREF
    - R G B
- 446 D.C. Characteristics
- 487 A.C. Characteristics
  - 7.1 CPU Interface Timing 7.1.1 SH-4 Interface Timing
  - 507.1.2 SH-3 Interface Timing
  - 527.1.3 MC68K Bus 1 Interface Timing (e.g. MC68000)
  - 547.1.4 MC68K Bus 2 Interface Timing (e.g. MC68030)
  - 567.1.5 PC Card Interface Timing
  - 587.1.6 Generic Interface Timing
  - 607.1.7 MIPS/ISA Interface Timing
  - 627.1.8 Philips Interface Timing (e.g. PR31500/PR31700)
    - 63The Philips interface has different clock input requirements as follows:
  - 647.1.9 Toshiba Interface Timing (e.g. TX3912)
    - 65The Toshiba interface has different clock input requirements as follows:
  - 667.1.10 Power PC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)
  - 687.2 Clock Input Requirements
    - When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).
  - 697.3 Memory Interface Timing 7.3.1 EDO-DRA M Read/Write/Read-Write Timing
  - 727.3.2 EDO-DRAM CAS Before RAS Refresh Timing
  - 747.3.3 EDO-DRAM Self-Refresh Timing
  - 757.3.4 FPM-DRAM Read/Write/Read-Write Timing
  - 787.3.5 FPM-DRAM CAS Before RAS Refresh Timing
  - 797.3.6 FPM-DRAM Self-Refresh Timing
  - 807.4 Power Sequencing 7.4.1 LCD Power Sequencing
    - Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock.
  - 817.4.2 Power Save Status
    - Page 76 Epson Research and Development
  - 827.5 Display Interface 7.5.1 4-Bit Single Monochrome Passive LCD Panel Timing
    - HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts
  - 847.5.2 8-Bit Single Monochrome Passive LCD Panel Timing
    - Figure 7-26: 8-Bit Single Monochrome Passive LCD Panel Timing
  - 867.5.3 4-Bit Single Color Passive LCD Panel Timing
    - Figure 7-28: 4-Bit Single Color Passive LCD Panel Timing
  - 887.5.4 8-Bit Single Color Passive LCD Panel Timing (Format 1)
    - Figure 7-30: 8-Bit Single Color Passive LCD Panel Timing (Format 1)
  - 907.5.5 8-Bit Single Color Passive LCD Panel Timing (Format 2)
    - Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2)
  - 927.5.6 16-Bit Single Color Passive LCD Panel Timing
    - Figure 7-34: 16-Bit Single Color Passive LCD Panel Timing
  - 947.5.7 8-Bit Dual Monochrome Passive LCD Panel Timing
    - Figure 7-36: 8-Bit Dual Monochrome Passive LCD Panel Timing
  - 967.5.8 8-Bit Dual Color Passive LCD Panel Timing
    - Figure 7-38: 8-Bit Dual Color Passive LCD Panel Timing
  - 987.5.9 16-Bit Dual Color Passive LCD Panel Timing
    - Figure 7-40: 16-Bit Dual Color Passive LCD Panel Timing
  - 1007.5.10 16-Bit TFT/D-TFD Panel Timing
    - Figure 7-42: 16-Bit TFT/D-TFD Panel Timing
    - HNDP = Horizontal Non-Display Period = HNDP1 + HNDP2= ((REG[05h] bits [4:0]) + 1)*8Ts
    - 101Figure 7-43: TFT/D-TFD A.C. Timing
  - 1037.5.11 CRT Timing
    - Figure 7-44: CRT Timing
    - HNDP = Horizontal Non-Display Period = HNDP1 + HNDP2= ((REG[05h] bits [4:0]) + 1)*8Ts
- 1058 Registers
  - 8.1 Register Mapping
  - 8.2 Register Descriptions
  - 8.2.1 Revision Code Register
  - 1068.2.2 Memory Configuration Registers
  - 1078.2.3 Panel/Monitor Configuration Registers
  - 1128.2.4 Display Configuration Registers
  - 1168.2.5 Clock Configuration Register
  - 8.2.6 Power Save Configuration Registers
  - 1178.2.7 Miscellaneous Registers
  - 1238.2.8 Look-Up Table Registers
  - 1248.2.9 Ink/Cursor Registers
    - 127Alternate FRM Register
- 1289 Display Buffer
  - 1299.1 Image Buffer
  - 9.2 Ink/Cursor Buffers
  - 9.3 Half Frame Buffer
    - Page 124 Epson Research and Development
- 13010 Display Configuration
  - 10.1 Display Mode Data Format
    - The following diagrams show the display mode data formats for a little-endian system.
      - Figure 10-1: 1/2/4/8 Bit-per-pixel Format Memory Organization
        Epson Research and Development Page 125
      - 131Figure 10-2: 15/16 Bit-per-pixel Format Memory Organization
  - 13210.2 Image Manipulation
- 13311 Look-Up Table Architecture
  - The following figures are intended to show the display data output path only.
  - 11.1 Monochrome Modes
    - The green Look-Up Table (LUT) is used for all monochrome modes. 1 Bit-per-pixel Monochrome mode
      - Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path
    - 2 Bit-per-pixel Monochrome Mode
      - Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path
    - 1344 Bit-per-pixel Monochrome Mode
      - Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path
  - 13511.2 Color Modes
    - 1 Bit-per-pixel Color Mode
      - Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path
    - 1362 Bit-per-pixel Color Mode
      - Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path
    - 1374 Bit-per-pixel Color Mode
      - Figure 11-6: 4 Bit-per-pixel Color Mode Data Output Path
    - 1388 Bit-per-pixel Color Mode
      - Figure 11-7: 8 Bit-per-pixel Color Mode Data Output Path
- 13912 Ink/Cursor Architecture
  - 12.1 Ink/Cursor Buffers
  - 12.2 Ink/Cursor Data Format
  - 14012.3 Ink/Cursor Image Manipulation 12.3.1 Ink Image
  - 12.3.2 Cursor Image
- 14113 SwivelView
- 14514 Clocking
  - 14.1 Maximum MCLK: PCLK Ratios
  - 14714.2 Frame Rate Calculation
    - The frame rate is calculated using the following formula:
    - Where:
  - 50ns
  - 14914.3 Bandwidth Calculation
  - 15150ns
- 15315 Power Save Modes
- 15416 Mechanical Data
  - Figure 16-1: Mechanical Drawing QFP15
- 161List of Tables
- 163List of Figures
- 1662 Initialization
  - 168Table 2-1: S1D13505 Initialization Sequence (Continued)
  - 1692.1 Miscellaneous
- 1703 Memory Models
  - 3.1 Display Buffer Location
    - 3.1.1 Memor y Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
    - 1713.1.2 Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
    - 3.1.3 M emory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
    - 1723.1.4 Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades)
    - 3.1.5 Memory Organization for Fifteen Bit-Per-Pixel (32768 Colors/16 Gray Shades)
    - 1733.1.6 Memory Organization for Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades)
- 1744 Look-Up Table (LUT)
  - 4.1 Look-Up Table Registers
  - 1754.2 Look-Up Table Organization
    - 15 bpp color
    - 179The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary.
      - 16 bpp color
    - Table 4-5: Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued)
- 1835 Advanced Techniques
  - 5.1 Virtual Display
    - 1845.1.1 Registers
    - 5.1.2 Examples
  - 1855.2 Panning and Scrolling
    - 1865.2.1 Registers
    - 1875.2.2 Examples
  - 1895.3 Split Screen
    - 5.3.1 Registers
    - 1915.3.2 Examples
- 1926 LCD Power Sequencing and Power Save Modes
  - 6.1 LCD Power Sequencing
    - 6.1.1 Registers
    - 1936.1.2 LCD Power Disable
  - 1946.2 Software Power Save
    - 1956.2.1 Registers
      - The Suspend Refresh Select bits should never be changed while in suspend mode.
  - 1966.3 Hardware Power Save
- 1977 Hardware Cursor/Ink Layer
  - 7.1 Introduction
  - 1987.2 Registers
  - 2007.3 Limitations
    - 7.3.1 Updating Hardware Cursor Addresses
    - 7.3.2 Reg[29h] And Reg[2Bh]
    - 7.3.3 Reg [30h]
    - 7.3.4 No Top/Left Clipping on Hardware Cursor
  - 7.4 Examples
- 2018 SwivelView
  - 8.1 Introduction To SwivelView
  - 8.2 S1D13505 SwivelView
  - 8.3 Registers
  - 2028.4 Limitations
  - 2038.5 Examples
- 2059 CRT Considerations
  - 9.1 Introduction
    - 9.1.1 CRT Only
    - 9.1.2 Simultaneous Display
- 20610 Identifying the S1D13505
- 20711 Hardware Abstraction Layer (HAL)
  - 11.1 Introduction
  - 11.2 Contents of the HAL_STRUCT
  - 20811.3 Using the HAL library
  - 11.4 API for 13505HAL
    - 209Table 11-1: HAL Functions (Continued)
  - 21011.5 Initialization
    - Table 11-1: HAL Functions (Continued)
    - See note from seSetInit().
    - 21211.5.1 General HAL Support
      - 215This call applies to the S1D13505 ISA evaluation cards only.
    - 21611.5.2 Advanced HAL Functions
      - 217It is assumed that the system has been properly initialized prior to calling seSplitInit().
      - The system must have been properly initi alized prior to calling seVirtInit()
      - seVirtInit() must be called before calling seVirtMove().
    - 21811.5.3 Register / Memory Access
      - 220If offset + count > memory size, this functio n will limit the writes to the end of memory.
      - If offset + (count*2) > memory size, this function will limit the writes to the end of memory.
      - If offset + (count*4) > memory size, this function will limit the writes to the end of memory.
    - 22111.5.4 Color Manipulation
    - 22311.5.5 Drawing
      - The Drawing section covers HAL functions that deal with displaying pixels, lines and shapes.
      - The 'SolidFill' argument is currently unused and is included for future considerations.
      - The SolidFill argument is currently unused and is included for future considerations.
    - 22511.5.6 Hardware Cursor
    - 22911.5.7 Ink Layer
    - 11.5.8 Power Save
  - 23211.6 Porting LIBSE to a new target platform
    - 23311.6.1 Building the LIBSE library for SH3 target example
    - 23411.6.2 Building the HAL library for the target example
    - 11.6.3 Building a complete application for the target example
- 23812 Sample Code
  - 12.1 Introduction
    - 12.1.1 Sample code using the S1D13505 HAL API
    - 24012.1.2 Sample code without using the S1D13505 HAL API
    - 24912.1.3 Header Files
      - 251The following header file defines the S1D13505 HAL registers.
      - 252The following header file defines the structures used in the S1D13505 HAL API.
  - 261Appendix A Supported Panel Values
    - A.1 Supported Panel Values
      - Table 12-2: Passive Single Panel @ 640x480 with 40MHz Pixel Clock
      - 262Table 12-3: Passive Dual Panel @ 640x480 with 40MHz Pixel Clock
      - Table 12-4: TFT Single Panel @ 640x480 with 25.175 MHz Pixel Clock
        263S1D13505F00A Register Summary X23A-R-001-04
        S1D13505F00A Register Summary
        Page 1 01/02/06
        264S1D13505F00A Register Summary X23A-R-001-04
        Page 2 01/02/06
26513505CFG Configuration Program
- Document Number: X23A-B-001-04
- 26913505CFG
  - S1D13505 Supported Evaluation Platforms
  - 270Installation
  - Usage
  - 27113505CFG Configuration Tabs
    - General Tab
    - 273Preferences Tab
    - 274Memory Tab
    - 276Clocks Tab
    - 279Panel Tab
    - 283CRT/TV Tab
    - 284Registers Tab
  - 28513505CFG Menus
    - Open...
    - 286Save
    - Save As...
    - 287Configure Multiple
    - 288Export
    - 289Enable Tooltips
    - ERD on the Web
    - About 13505CFG
  - 293 13505SHOW
    - 29413505SHOW Examples
  - 301 13505SPLT
    - 30213505SPLT Example
  - 307 13505VIRT
    - 30913505VIRT Example
  - 313 13505PLAY
    - 31513505PLAY Example
    - 316Scripting
  - 321 13505BMP
    - 322Hardware Cursor/Ink Layer
    - Table 1: 4 Bpp to 2 Bpp Translation
    - 32313505BMP Examples
  - 329 13505PWR
    - 33013505PWR Examples
333Windows CE 2.x Display Drivers
- Document Number: X23A-E-001-06
- 335WINDOWS CE 2.x DISPLAY DRIVERS
  - 336Example Driver Builds
  - 342Installation for CEPC Environment
  - 343Configuration
    - Compile Switches
    - 344Mode File
- 349Wind River WindML v2.0 DISPLAY DRIVERS
  - 350Building a WindML v2.0 Display Driver
353Wind River UGL v1.2 Display Drivers
- Document Number: X23A-E-003-02
- 355Wind River UGL v1.2 Display Drivers
  - 356Building a UGL v1.2 Display Driver
359Windows CE 3.x Display Drivers
- Document Number: X23A-E-006-01
- 361WINDOWS CE 3.x DISPLAY DRIVERS
  - 362Example Driver Builds
  - 368Installation for CEPC Environment
  - 369Configuration
    - Compile Switches
    - 370Mode File
    - 371Resource Management Issues
    - 3811.1 Features
  - 3822 Installation and Configuration
  - 3833 LCD Interface Pin Mapping
    - Table 3-1: LCD Signal Connector (J6)
  - 3844 CPU/Bus Interface Connector Pinouts
    - Table 4-1: CPU/BUS Connector (H1) Pinout
  - 3865 Host Bus Interface Pin Mapping
  - 3876 Technical Description
    - 6.1 ISA Bus Support
    - 6.2 Non-ISA Bus Support
    - 3906.8 Color TFT/D-TFD LCD Panel Support
    - 6.9 CRT Support
    - 6.10 Power Save Modes
    - 6.11 Adjustable LCD Panel Negative Power Supply
    - 6.12 Adjustable LCD Panel Positive Power Supply
    - 3916.13 CPU/Bus Interface Header Strips
    - 6.14 Schematic Notes
  - 3927 Parts List
    - Page 20 Epson Research and Development
  - 3948 Schematic Diagrams
    - Figure 1: S1D13505B00C Schematic Diagram (1 of 4)
      - Epson Research and Development Page 21
    - 395Figure 2: S1D13505B00C Schematic Diagram (2 of 4)
      - Page 22 Epson Research and Development
    - 396Figure 3: S1D13505B00C Schematic Diagram (3 of 4)
      - Epson Research and Development Page 23
    - 397Figure 4: S1D13505B00C Schematic Diagram (4 of 4)
  - S5U13505-D9000
399Evaluation Board User Manual
- Document Number: X23A-G-002-04
- 4062 Features
  - 2.1 S1D13505 Embedded RAMDAC LCD/CRT Controller
  - 2.1.1 Display Buffer
  - 4072.1.2 LCD Display Support
    - 408Table 2-1: LCD Connector Pinout
  - 4092.1.3 Touchscreen Support
  - 2.1.4 CRT Support
  - 2.1.5 Jumper Selection
  - 2.1.6 Adjustable LCD BIAS Power Supply
- 4113 D9000 Specifics
  - 3.1 Interface Signals
  - 3.1.1 Connector Pinout for Channel A6 and A7
    - Table 3-1: Connectors Pinout for Channel A7
    - 412Table 3-1: Connectors Pinout for Channel A7 (Continued)
    - 413Table 3-2: Connectors Pinout for Channel A6
    - 414Table 3-2: Connectors Pinout for Channel A6 (Continued)
  - 4153.1.2 Memory Address (CS#, M/R#) Decoding
  - 3.2 FPGA Code Functionality
  - 3.3 Board Dimensions
- 4164 Parts List
  - Epson Research and Development Page 19
  - Evaluation Board User Manual S5U13505-D9000 Issue Date: 01/02/05 X23A-G-002-04
- 4175 Schematic Diagrams
  - Figure 5-1: S5U13505-D9000 Schematic Diagram (1 of 3)
    - Page 20 Epson Research and Development
    - S5U13505-D9000 Evaluation Board User Manual X23A-G-002-04 Issue Date: 01/02/05
  - 418Figure 5-2: S5U13505-D9000 Schematic Diagram (2 of 3)
    - Epson Research and Development Page 21
    - Evaluation Board User Manual S5U13505-D9000 Issue Date: 01/02/05 X23A-G-002-04
  - 419Figure 5-3: S5U13505-D9000 Schematic Diagram (3 of 3)
- 4231 S1D13505 Power Consumption
  - 1.1 Conditions
- 4242 Summary
- 4322 Interfacing to the PR31500/PR31700
  - 4333.1 PR31500/PR31700 Host Bus Interface Pin Mapping
  - 4343.2 PR31500/PR31700 Host Bus Interface Signals
- 4354 Direct Connection to the Philips PR31500/PR31700
  - 4374.3 Memory Mapping and Aliasing
- 4385 System Design Using the IT8368E PC Card Buffer
  - 5.1 Hardware Description
  - 4395.2 IT8368E Configuration
  - 5.3 S1D13505 Configuration
- 4406 Software
- 4417 References
  - 7.1 Documents
  - 7.2 Document Sources
- 4428 Technical Support
  - 8.1 EPSON LCD/CRT Controllers (S1D13505)
  - 8.3 ITE IT8368E
  - 8.2 Philips MIPS PR31500/PR31700 Processor
- 4502 Interfacing to the PC Card Bus
  - 2.1 The PC Card System Bus
    - 2.1.1 PC Card Overview
    - 2.1.2 Memory Access Cycles
      - 452Figure 2-2: illustrates a typical memory access write cycle on the PC Card bus.
      - Figure 2-2: PC Card Write Cycle
  - 4533.1 PC Card Host Bus Interface Pin Mapping
  - 4543.2 PC Card Host Bus Interface Signals
- 4554 PC Card to S1D13505 Interface
  - 456The following diagram shows a typical implementation of the PC Card to S1D13505 interface.
  - Figure 4-1: Typical Implementation of PC Card to S1D13505 Interface
  - 4574.3 Performance
  - 4584.4 Register/Memory Mapping
  - 4617.2 PC Card Standard
- 4702 Interfacing to the VR4102/VR4111
  - 2.1 The NEC VR4102/VR4111 System Bus
    - 4712.1.2 LCD Memory Access Cycles
  - 4733.2 Host Bus Interface Signals Descriptions
- 4744 VR4102/VR4111 to S1D13505 Interface
  - Figure 4-1: NEC VR4102/VR4111 to S1D13505 Configuration Schematic
  - 4754.3 NEC VR4102/VR4111 Configuration
  - 4787.2 NEC Electronics Inc. (VR4102/VR4111).
- 4862 Interfacing to the MPC821
  - 2.1 The MPC8xx System Bus
  - 2.2 MPC821 Bus Overview
    - 4872.2.1 Normal (Non-Burst) Bus Transactions
    - 4882.2.2 Burst Cycles
  - 4892.3 Memory Controller Module
    - 2.3.1 General-Purpose Chip Select Module (GPCM)
    - 4902.3.2 User-Programmable Machine (UPM)
  - 4913.1 PowerPC Host Bus Interface Pin Mapping
  - 4923.2 PowerPC Host Bus Interface Signals
- 4934 MPC821 to S1D13505 Interface
  - 4944.2 Hardware Connections
    - 495Table 4-1: List of Connections from MPC821ADS to S1D13505 (Continued)
  - 4964.3 S1D13505 Hardware Configuration
  - 4.4 Register/Memory Mapping
  - 4974.5 MPC821 Chip Select Configuration
  - 4984.6 Test Software
  - 5017.2 Motorola MPC821 Processor
    - Motorola Design Line, (800) 521-6274. Local Motorola sales office or authorized di stributor.
- 5102 Interfacing to the TX3912
  - 5113.1 TX3912 Host Bus Interface Pin Mapping
  - 5123.2 TX3912 Host Bus Interface Signals
- 5134 Direct Connection to the Toshiba TX3912
  - 5154.3 Memory Mapping and Aliasing
- 5165 System Design Using the IT8368E PC Card Buffer
  - 5.1 Hardware Description
  - 5175.2 IT8368E Configuration
  - 5.3 S1D13505 Configuration
- 5186 Software
- 5197 References
  - 7.1 Documents
  - 7.2 Document Sources
- 5208 Technical Support
  - 8.1 EPSON LCD/CRT Controllers (S1D13505)
  - 8.2 Toshiba MIPS TX3912 Processor 8.3 ITE IT8368E
- 5282 Interfacing to the NEC VR4121
  - 2.1 The NEC VR4121 System Bus
    - 5292.1.2 LCD Memory Access Cycles
  - 5313.2 Host Bus Interface Signal Descriptions
- 5324 VR4121 to S1D13505 Interface
  - Figure 4-1: NEC VR4121 to S1D13505 Configuration Schematic
  - 5334.3 NEC VR4121 Configuration
  - 5344.4 Memory Mapping and Aliasing
  - 5377.2 NEC Electronics Inc. (VR4121).
- 5462 Interfacing to the NEC V832
  - 2.1 The NEC V832 System Bus
    - 5472.1.2 Access Cycles
  - 5493.2 Host Bus Interface Signal Descriptions
- 5504 V832 to S1D13505 Interface
  - Note:
  - Figure 4-1: NEC V832 to S1D13505 Configuration Schematic
  - 5524.3 NEC V832 Configuration
  - 5534.4 Memory Mapping and Aliasing
    - Table 4-3: NEC V832 IO Address Range For Each CSn Line
  - 5567.2 NEC Electronics Inc. (V832).

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