S1D13505F00A Register Summary X23A-R-001-04Page 1 01/02/06
Notes
1 These bits are used to identify the S1D13505. For the S1D13505 the product code should be 3. The host
interface must be enabled before reading this register (set REG[1B] b7=0).
2 N/A bits should be written 0.
Reserved bits must be written 0.
REG[00h] REVISION CODE REGISTER 1 (For S1D13505: Product Code=000011b, Revision Code=00b)RO
Product Code Revision Code
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
REG[01h] MEMORY CONFIGURATION REGISTER 1/0 RW
n/a 2Refresh Rate 3n/a WE# Control n/a Memory
Type
Bit 2 Bit 1 Bit 0
REG[02h] PANEL TYPE REGISTER 1/0 RW
EL Panel
Enable n/a Panel Data Width 4Panel Data
Format Slct Color/Mono
Panel Slct Dual/Single
Panel Slct TFT/Passive
LCD Pan Slct
Bit 1 Bit 0
REG[03h] MOD RATE REGISTER RW
n/a n/a MOD Rate
Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0
REG[04h] HORIZONTAL DISPLAY WIDTH REGISTER RW
n/a Horizontal Display Width = 8(REG + 1)
Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0
REG[05h] HORIZONTAL NON-DISPLAY PERIOD REGISTER RW
n/a n/a n/a Horizontal Non-Display Period = 8(REG + 1)
Bit 4 Bit 3 Bit 2 B it 1 Bit 0
REG[06h] HRTC/FPLINE START POSITION REGISTER RW
n/a n/a n/a HRTC/FPLINE Start Position = 8(REG + 1) - 2
Bit 4 Bit 3 Bit 2 B it 1 Bit 0
REG[07h] HRTC/FPLINE PULSE WIDTH REGISTER RW
HRTC
Polarity Slct FPLINE
Polarity Slct n/a n/a HRTC/FPLINE Pulse Width = 8(REG + 1)
Bit 3 Bit 2 Bit 1 Bit 0
REG[08h] VERTICAL DISPLAY HEIGHT REGISTER 0 RW
Vertical Display Height = (REG + 1)
Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0
REG[09h] VERTICAL DISPLAY HEIGHT REGISTER 1 RW
n/a n/a n/a n/a n/a n/a Vertical Display Height
Bit 9 Bit 8
REG[0Ah] VERTICAL NON-DISPLAY PERIOD REGISTER RW
VNDP
Status (RO) n/a Vertical Non-Display Period (VNDP) = (REG + 1)
Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0
REG[0Bh] VRTC/FPFRAME START POSITION REGISTER RW
n/a n/a VRTC/FPFRAME Start Position = (REG + 1)
Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0
REG[0Ch] VRTC/FPFRAME PULSE WIDTH REGISTER RW
VRTC
Polarity Slct FPFRAME
Polarity Slct n/a n/a n/a VRTC/FPFRAME Pulse Width = (REG + 1)
Bit 2 Bit 1 Bit 0
REG[0Dh] DISPLAY MODE REGISTER RW
Hardware
Portrait
Mode
Enable
Simultaneous Display 5
Option Select Bit-per-pixel Select6
CRT Enable LCD Enable
Bit 1 Bit 0 Bit 2 B it 1 Bit 0
REG[0Eh] SCREEN 1 LINE COMPARE REGISTER 0 RW
Screen 1 Line Compare
Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0
REG[0Fh] SCREEN 1 LINE COMPARE REGISTER 1 RW
n/a n/a n/a n/a n/a n/a Screen 1 Line Compare
Bit 9 Bit 8
REG[10h] SCREEN 1 DISPLAY START ADDRESS REGISTER 0 RW
Screen 1 Start Address
Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0
REG[11h] SCREEN 1 DISPLAY START ADDRESS REGISTER 1 RW
Screen 1 Start Address
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[12h] SCREEN 1 DISPLAY START ADDRESS REGISTER 2 RW
n/a n/a n/a n/a Screen 1 Start Address
Bit 19 Bit 18 Bit 17 Bit 16
REG[13h] SCREEN 2 DISPLAY START ADDRESS REGISTER 0 RW
Screen 2 Start Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[14h] SCREEN 2 DISPLAY START ADDRESS REGISTER 1 RW
Screen 2 Start Address
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[15h] SCREEN 2 DISPLAY START ADDRESS REGISTER 2 RW
n/a n/a n/a n/a Screen 2 Start Address
Bit 19 Bit 18 Bit 17 Bit 16
REG[16h] MEMORY ADDRESS OFFSET REGISTER 0 RW
Memory Address Offset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[17h] MEMORY ADDRESS OFFSET REGISTER 1 RW
n/a n/a n/a n/a n/a Memory Address Offset
Bit 10 Bit 9 Bit 8
REG[18h] PIXEL PANNING REGISTER RW
Screen 2 Pixel Panning Screen 1 Pixel Panning
Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0
REG[19h] CLOCK CONFIGURATION REGISTER RW
Reserved n/a n/a n/a n/a MCLK
Divide Slct PCLK Divide 7 Slct
Bit 1 Bit 0
REG[1Ah] POWER SAVE CONFIGURATION REGISTER RW
Power Save
Status RO n/a n/a n/a LCD Power
Disable Suspend Refresh Select 8Software
Suspend En
Bit 1 Bit 0
REG[1Bh] MISCELLANIOUS REGISTER RW
Host
Interface
Disable n/a n/a n/a n/a n/a n/a Half Frame
Buffer
Disable
REG[1Ch] MD CONFIGURATION READBACK REGISTER 0 RO
MD7
Status MD6
Status MD5
Status MD4
Status MD3
Status MD2
Status MD1
Status MD0
Status
REG[1Dh] MD CONFIGURATION READBACK REGISTER 1 RO
MD15
Status MD14
Status MD13
Status MD12
Status MD11
Status MD10
Status MD9
Status MD8
Status
REG[1Eh] GENERAL IO PINS CONFIGURATION REGISTER 0 RW
n/a n/a n/a n/a GPIO3 Pin
IO Config GP IO2 Pin
IO Config GPIO1 Pin
IO Config n/ a
REG[1Fh] GENERAL IO PINS CONFIGURATION REGISTER 1 RW
n/a n/a n/a n/a n/a n/a n/a n/a
REG[20h] GENERAL IO PINS CONTROL REGISTER 0 RW
n/a n/a n/a n/a GPIO3 Pin
IO Status GPIO2 Pin
IO Status GPIO1 Pin
IO Status n/a
REG[21h] GENERAL IO PINS CONTROL REGISTER 1 RW
GPO
Control n/a n/a n/a n/a n/a n/a n/a
REG[22h] PERFORMANCE ENHANCEMENT REGISTER 0 RW
Reserved RC Timing Value 9RAS#-to-
CAS#
Delay 10
RAS# Precharge 11 Timing Reserved Reserved
Bit 1 Bit 0 Bit 1 Bit 0
REG[23h] PERFORMANCE ENHANCEMENT REGISTER 1 RW
Display FIFO
Disable CPU to Memory Wait State Display FIFO Threshold
Bit 1Bit 0Bit 4Bit 3Bit 2Bit 1Bit 0
REG[24h] LOOK-UP TABLE ADDRESS REGISTER RW
Look-Up Table Address
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[26h] LOOK-UP TABLE DATA REGISTER RW
Look-Up Table Data n/a n/a n/a n/a
Bit 3Bit 2Bit 1Bit 0
REG[27h] INK/CURSOR CONTROL REGISTER RW
Ink/Cursor Mode n/a n/a Cursor High Threshold
Bit 1Bit 0 Bit 3Bit 2Bit 1Bit 0
REG[28h] CURSOR X POSITION REGISTER 0 RW
Cursor X Position
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[29h] CURSOR X POSITION REGISTER 1 RW
Reserved n/a n/a n/a n/a n/a Cursor X Position
Bit 9 Bit 8
REG[2Ah] CURSOR Y POSITION REGISTER 0 RW
Cursor Y Position
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[2Bh] CURSOR Y POSITION REGISTER 1 RW
Reserved n/a n/a n/a n/a n/a Cursor Y Position
Bit 9 Bit 8
REG[2Ch] INK/CURSOR COLOR 0 REGISTER 0 RW
Cursor Color 0
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[2Dh] INK/CURSOR COLOR 0 REGISTER 1 RW
Cursor Color 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[2Eh] INK/CURSOR COLOR 1 REGISTER 0 RW
Cursor Color 1
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[2Fh] INK/CURSOR COLOR 1 REGISTER 1 RW
Cursor Color 1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[30h] INK/CURSOR START ADDRESS SELECT REGISTER RW
Ink/Cursor Start Address Select 12
Bit 7 WOBit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[31h] ALTERNATE FRM REGISTER RW
Alternate Frame Range Modulation Select
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
S1D13505F00A Register Summary