Philips S1D13505 2.1.2 LCD Memory Access Cycles

Epson Research and Development Page 9
Vancouver Design Center
Interfacing to the NEC VR4102/VR4111™ Microprocessors S1D13505
Issue Date: 01/02/05 X23A-G-007-06
2.1.2 LCD Memory Access Cycles
Once an address in the LCD block of memory is placed on the external address bus
(ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable
signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low
to insert wait states into the cycle. The high byt e enable (SHB#) in conjunction with address
bit 0 allows for byte steering.
The following figure illustrates typical NEC VR4102/VR4111 memory read and write
cycles to the LCD controller interface.
Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles
TCLK
ADD[25:0]
LCDCS#
WR#,RD#
LCDRDY
VALID
VALID
VALID
Hi-Z Hi-Z
D[15:0]
D[15:0]
(write)
(read)
SHB#