Philips S1D13505 2.3 Memory Controller Module

Epson Research and Development Page 11
Vancouver Design Center
Interfacing to the Motorola MPC821 Microprocessor S1D13505
Issue Date: 01/02/05 X23A-G-008-05
If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI)
simultaneously with TA, and the processor will revert to normal bus cycles for the
remaining data transfers.
Burst cycles are mainly intended to facilitate c ache line fills from program or data memory.
They are normally not used for transfers to/from IO peripheral devices such as the
S1D13505, therefore the interfaces described in this document do not attempt to support
burst cycles. However, the example interfaces include circuitry to detect the assertion of
BDIP and respond with BI if caching is accidently enabled for the S1D13505 address spa ce.
2.3 Memory Controller Module
2.3.1 General-Purpose Chip Select Module (GPCM)
The General-Purpose Chip Select Module (GPCM) is used to control memory and
peripheral devices which do not require special timing o r add ress mult iplexin g. In additio n
to the chip select output, it can generate active-low Output Enable (OE) and Write Enable
(WE) signals compatible with most memory and x86-style peripherals. The MPC821 bus
controller also provides a Read/Write (RD/WR) signal which is compatible with most 6 8K
peripherals.
The GPCM is controlled by the values programmed into the Base Register (BR) and Option
Register (OR) of the respective chip select. The Option Register sets the base address, the
block size of the chip select, and controls the following timing parameters:
•The ACS bit field allows the chip select assertion to be delayed by 0, ¼, or ½ clock
cycle with respect to the address bus valid.
���The CSNT bit causes chip select and WE to be negated ½ clock cycle earlier than
normal.
•The TRLX (relaxed timing) bit will insert an additional one clock delay between
assertion of the address bus and chip se lect. This accommodates memory and
peripherals with long setup times.
•The EHTR (Extended hold time) bit will insert an additional 1 clock delay on the first
access to a chip select.
•Up to 15 wait states may be insert ed, or the peripheral can terminate the bus cycle itself
by asserting TA (Transfer Acknowledge).
•Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its
memory space is addressed by the processor core.