Page 8 Epson Research and Development
Vancouver Design Center
S5U13505-D9000 Evaluation Board User Manual
X23A-G-002-04 Issue Date: 01/02/05
2 Features
•S1D13505 Embedded RAMDAC LCD/CRT controller.
•4/8-bit monochrome or 4/8/16-bit color LCD interface for single-panel, single-drive displays.
•8-bit monochrome or 8/16-bit color LCD interface for dual-panel, dual-drive displays.
•Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported to 64K colors (16-bit
data).
•Direct CRT support to 64K colors using the S1D13505 embedded RAMDAC.
•Up to 16 shades of gray using Frame Rate Modulatio n (FRM) on monochrome passive LCD
panels.
•Up to 4096 colors on color passive LCD panels; three 256x4 Look-Up Tables (LUT) are used
to map 1/2/4/8 bpp modes into these colors, 15/16 bpp modes are mapped directly using the
four most significant bits of the red, green and blue colors.
•Up to 64K colors on TFT/D-TFD and CRT; three 256x4 Look-Up Tables are used to map
1/2/4/8 bpp modes into 4096 colors, 15/16 bpp modes are mapped directly.
•On-board 2M byte EDO-DRAM display buffer.
•On-board adjustable LCD bias voltage power supply.
•SmallTypeZ x 2 form factor (requires two side-by-side SmallTypeZ slots).

2.1 S1D13505 Embedded RAMDAC LCD/CRT Controller

The S1D13505 is a low cost, low power, color/monochrome LCD/CRT controller with an embedded
RAMDAC capable of interfacing to a wide range of CPUs and LCD displays.
The S1D13505 supports LCD interfaces with data widths up to 16-bits. Using Frame Rate
Modulation (FRM), it can display 16 shades of gray on monochrome panels, up to 4096 colors on
passive panels and 64K colors on active matrix TFT/D-TFD. CRT support is handled through the
use of an embedded RAMDAC allowing simultaneous display of both the CRT and LCD displays.
In this design, the S1D13505 has a 3.3V supply voltage for both logic and the embedded RAMDAC.
For complete details on register functionality and programming, refer to the S1D13505 Hardware
Functional Specification, document number X23A-A-001-xx, and the S1D13505 Programming
Notes and Examples, document number X23A-G-003-xx.

2.1.1 Display Buffer

The S1D13505 supports a 512K byte or 2M byte FPM-DRAM or EDO-DRAM display buffer. On
the S5U13505-D9000 evaluation board a 1Mx16 EDO-DRAM (2M byte) is used to prov ide memory
for all supported display resolutions, and when smaller display sizes are used, to provide multiple
“pages” of memory.