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GRAPHICS S1D13505
S1D13505 EMBEDDED RAMDAC LCD/CRT CONTROLLER October 2001
X23A-C-002-15 2
GRAPHICS S1D13505
S1D13505
CPU
Driver
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1.1 Scope
1.2 Overview Description
2 Features
2.1 Memory Interface
2.2 CPU Interface
2.3 Display Support
2.4 Display Modes
2.5 Display Features
2.6 Clock Source
2.7 Miscellaneous
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3 Typical System Implementation Diagrams
Figure 3-1: Typical System Diagram (SH-4 Bus)
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Figure 3-2: Typical System Diagram (SH-3 Bus)
SH-4
Figure 3-3: Typical System Diagram (MC68K Bus 1, 16-Bit 68000)
Figure 3-4: Typical System Diagram (MC68K Bus 2, 32-Bit 68030)
MC68000
MC68030
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Figure 3-5: Typical System Diagram (Generic Bus)
Figure 3-6: Typical System Diagram (NEC VR41xx (MIPS) Bus)
Generic
MIPS
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Figure 3-7: Typical System Diagram (Philips PR31500/PR3 1700 Bus)
Figure 3-8: Typical System Diagram (Toshiba TX3912 Bu s)
PR31500 BUS
/PR31700
Philips
Figure 3-9: Typical System Diagram (Power PC Bus)
Figure 3-10: Typical System Diagram (PC Card (PCMCIA) Bus)
PowerPC
256Kx16
PC Card
4 Internal Description
4.1 Block Diagram Showing Datapaths
4.2 Block Descriptions 4.2.1 Register
4.2.2 Host Interface
4.2.3 CPU R/W
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5 Pins
5.1 Pinout Diagram
Figure 5-1: Pinout Diagram
S1D13505
5.2 Pin Description
Key:
5.2.1 Host Interface
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5.2.2 Memory Interface
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5.2.3 LCD Interface
5.2.4 CRT Interface
Table 5-2: LCD
5.2.5 Miscellaneous
5.3 Summary of Configuration Options
5.4 Multiple Function Pin Mapping
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}
5.5 CRT Interface
The following figure shows the external circuitry for the CRT interface.
Figure 5-3: External Circuitry for CRT Interface
4.6 mA
6 D.C. Characteristics
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7 A.C. Characteristics
7.1 CPU Interface Timing 7.1.1 SH-4 Interface Timing
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7.1.2 SH-3 Interface Timing
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7.1.3 MC68K Bus 1 Interface Timing (e.g. MC68000)
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7.1.4 MC68K Bus 2 Interface Timing (e.g. MC68030)
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7.1.5 PC Card Interface Timing
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7.1.6 Generic Interface Timing
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7.1.7 MIPS/ISA Interface Timing
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7.1.8 Philips Interface Timing (e.g. PR31500/PR31700)
The Philips interface has different clock input requirements as follows:
7.1.9 Toshiba Interface Timing (e.g. TX3912)
The Toshiba interface has different clock input requirements as follows:
7.1.10 Power PC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)
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7.2 Clock Input Requirements
When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).
7.3 Memory Interface Timing 7.3.1 EDO-DRA M Read/Write/Read-Write Timing
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7.3.2 EDO-DRAM CAS Before RAS Refresh Timing
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7.3.3 EDO-DRAM Self-Refresh Timing
7.3.4 FPM-DRAM Read/Write/Read-Write Timing
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7.3.5 FPM-DRAM CAS Before RAS Refresh Timing
7.3.6 FPM-DRAM Self-Refresh Timing
7.4 Power Sequencing 7.4.1 LCD Power Sequencing
Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock.
7.4.2 Power Save Status
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7.5 Display Interface 7.5.1 4-Bit Single Monochrome Passive LCD Panel Timing
HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts
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7.5.2 8-Bit Single Monochrome Passive LCD Panel Timing
Figure 7-26: 8-Bit Single Monochrome Passive LCD Panel Timing
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7.5.3 4-Bit Single Color Passive LCD Panel Timing
Figure 7-28: 4-Bit Single Color Passive LCD Panel Timing
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7.5.4 8-Bit Single Color Passive LCD Panel Timing (Format 1)
Figure 7-30: 8-Bit Single Color Passive LCD Panel Timing (Format 1)
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7.5.5 8-Bit Single Color Passive LCD Panel Timing (Format 2)
Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2)
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7.5.6 16-Bit Single Color Passive LCD Panel Timing
Figure 7-34: 16-Bit Single Color Passive LCD Panel Timing
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7.5.7 8-Bit Dual Monochrome Passive LCD Panel Timing
Figure 7-36: 8-Bit Dual Monochrome Passive LCD Panel Timing
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7.5.8 8-Bit Dual Color Passive LCD Panel Timing
Figure 7-38: 8-Bit Dual Color Passive LCD Panel Timing
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7.5.9 16-Bit Dual Color Passive LCD Panel Timing
Figure 7-40: 16-Bit Dual Color Passive LCD Panel Timing
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7.5.10 16-Bit TFT/D-TFD Panel Timing
Figure 7-42: 16-Bit TFT/D-TFD Panel Timing
HNDP = Horizontal Non-Display Period = HNDP1 + HNDP2= ((REG[05h] bits [4:0]) + 1)*8Ts
Figure 7-43: TFT/D-TFD A.C. Timing
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7.5.11 CRT Timing
Figure 7-44: CRT Timing
HNDP = Horizontal Non-Display Period = HNDP1 + HNDP2= ((REG[05h] bits [4:0]) + 1)*8Ts
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8 Registers
8.1 Register Mapping
8.2 Register Descriptions
8.2.1 Revision Code Register
8.2.2 Memory Configuration Registers
8.2.3 Panel/Monitor Configuration Registers
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8.2.4 Display Configuration Registers
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8.2.5 Clock Configuration Register
8.2.6 Power Save Configuration Registers
8.2.7 Miscellaneous Registers
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8.2.8 Look-Up Table Registers
8.2.9 Ink/Cursor Registers
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Alternate FRM Register
9 Display Buffer
9.1 Image Buffer
9.2 Ink/Cursor Buffers
9.3 Half Frame Buffer
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10 Display Configuration
10.1 Display Mode Data Format
The following diagrams show the display mode data formats for a little-endian system.
Figure 10-1: 1/2/4/8 Bit-per-pixel Format Memory Organization
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Figure 10-2: 15/16 Bit-per-pixel Format Memory Organization
10.2 Image Manipulation
11 Look-Up Table Architecture
The following figures are intended to show the display data output path only.
11.1 Monochrome Modes
The green Look-Up Table (LUT) is used for all monochrome modes. 1 Bit-per-pixel Monochrome mode
Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path
4 Bit-per-pixel Monochrome Mode
Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path
11.2 Color Modes
1 Bit-per-pixel Color Mode
Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path
2 Bit-per-pixel Color Mode
Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path
4 Bit-per-pixel Color Mode
Figure 11-6: 4 Bit-per-pixel Color Mode Data Output Path
8 Bit-per-pixel Color Mode
Figure 11-7: 8 Bit-per-pixel Color Mode Data Output Path
12 Ink/Cursor Architecture
12.1 Ink/Cursor Buffers
12.2 Ink/Cursor Data Format
12.3 Ink/Cursor Image Manipulation 12.3.1 Ink Image
12.3.2 Cursor Image
13 SwivelView
13.1 Concept
13.2 Image Manipulation in SwivelView
13.3 Physical Memory Requirement
13.4 Limitations
14 Clocking
14.1 Maximum MCLK: PCLK Ratios
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14.2 Frame Rate Calculation
The frame rate is calculated using the following formula:
Where:
50ns
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14.3 Bandwidth Calculation
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50ns
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15 Power Save Modes
16 Mechanical Data
Figure 16-1: Mechanical Drawing QFP15
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List of Tables
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List of Figures
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2 Initialization
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Table 2-1: S1D13505 Initialization Sequence (Continued)
2.1 Miscellaneous
3 Memory Models
3.1 Display Buffer Location
3.1.1 Memor y Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
3.1.2 Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
3.1.3 M emory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
3.1.4 Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades)
3.1.5 Memory Organization for Fifteen Bit-Per-Pixel (32768 Colors/16 Gray Shades)
3.1.6 Memory Organization for Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades)
4 Look-Up Table (LUT)
4.1 Look-Up Table Registers
4.2 Look-Up Table Organization
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15 bpp color
The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary.
16 bpp color
Table 4-5: Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued)
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5 Advanced Techniques
5.1 Virtual Display
5.1.1 Registers
5.1.2 Examples
5.2 Panning and Scrolling
5.2.1 Registers
5.2.2 Examples
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5.3 Split Screen
5.3.1 Registers
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5.3.2 Examples
6 LCD Power Sequencing and Power Save Modes
6.1 LCD Power Sequencing
6.1.1 Registers
6.1.2 LCD Power Disable
6.2 Software Power Save
6.2.1 Registers
The Suspend Refresh Select bits should never be changed while in suspend mode.
6.3 Hardware Power Save
7 Hardware Cursor/Ink Layer
7.1 Introduction
7.2 Registers
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7.3 Limitations
7.3.1 Updating Hardware Cursor Addresses
7.3.2 Reg[29h] And Reg[2Bh]
7.3.3 Reg [30h]
7.3.4 No Top/Left Clipping on Hardware Cursor
8 SwivelView
8.1 Introduction To SwivelView
8.2 S1D13505 SwivelView
8.3 Registers
8.4 Limitations
8.5 Examples
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9 CRT Considerations
9.1 Introduction
9.1.1 CRT Only
9.1.2 Simultaneous Display
10 Identifying the S1D13505
11 Hardware Abstraction Layer (HAL)
11.1 Introduction
11.2 Contents of the HAL_STRUCT
11.3 Using the HAL library
11.4 API for 13505HAL
Table 11-1: HAL Functions (Continued)
11.5 Initialization
Table 11-1: HAL Functions (Continued)
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See note from seSetInit().
11.5.1 General HAL Support
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This call applies to the S1D13505 ISA evaluation cards only.
11.5.2 Advanced HAL Functions
It is assumed that the system has been properly initialized prior to calling seSplitInit().
The system must have been properly initi alized prior to calling seVirtInit()
seVirtInit() must be called before calling seVirtMove().
11.5.3 Register / Memory Access
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If offset + count > memory size, this functio n will limit the writes to the end of memory.
If offset + (count*2) > memory size, this function will limit the writes to the end of memory.
If offset + (count*4) > memory size, this function will limit the writes to the end of memory.
11.5.4 Color Manipulation
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11.5.5 Drawing
The Drawing section covers HAL functions that deal with displaying pixels, lines and shapes.
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The 'SolidFill' argument is currently unused and is included for future considerations.
The SolidFill argument is currently unused and is included for future considerations.
11.5.6 Hardware Cursor
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11.5.7 Ink Layer
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11.5.8 Power Save
11.6 Porting LIBSE to a new target platform
11.6.1 Building the LIBSE library for SH3 target example
11.6.2 Building the HAL library for the target example
11.6.3 Building a complete application for the target example
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12 Sample Code
12.1 Introduction
12.1.1 Sample code using the S1D13505 HAL API
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12.1.2 Sample code without using the S1D13505 HAL API
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12.1.3 Header Files
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The following header file defines the S1D13505 HAL registers.
The following header file defines the structures used in the S1D13505 HAL API.
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Appendix A Supported Panel Values
A.1 Supported Panel Values
Table 12-2: Passive Single Panel @ 640x480 with 40MHz Pixel Clock
Table 12-3: Passive Dual Panel @ 640x480 with 40MHz Pixel Clock
Table 12-4: TFT Single Panel @ 640x480 with 25.175 MHz Pixel Clock
S1D13505F00A Register Summary X23A-R-001-04
S1D13505F00A Register Summary
Page 1 01/02/06
S1D13505F00A Register Summary X23A-R-001-04
Page 2 01/02/06
13505CFG Configuration Program
Document Number: X23A-B-001-04
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13505CFG
S1D13505 Supported Evaluation Platforms
Installation
Usage
13505CFG Configuration Tabs
General Tab
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Preferences Tab
Memory Tab
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Clocks Tab
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Panel Tab
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CRT/TV Tab
Registers Tab
13505CFG Menus
Open...
Save
Save As...
Configure Multiple
Export
Enable Tooltips
ERD on the Web
About 13505CFG
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13505SHOW
13505SHOW Examples
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13505SPLT
13505SPLT Example
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13505VIRT
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13505VIRT Example
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13505PLAY
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13505PLAY Example
Scripting
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13505BMP
Hardware Cursor/Ink Layer
Table 1: 4 Bpp to 2 Bpp Translation
13505BMP Examples
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13505PWR
13505PWR Examples
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Windows CE 2.x Display Drivers
Document Number: X23A-E-001-06
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WINDOWS CE 2.x DISPLAY DRIVERS
Example Driver Builds
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Installation for CEPC Environment
Configuration
Compile Switches
Mode File
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Wind River WindML v2.0 DISPLAY DRIVERS
Building a WindML v2.0 Display Driver
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Wind River UGL v1.2 Display Drivers
Document Number: X23A-E-003-02
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Wind River UGL v1.2 Display Drivers
Building a UGL v1.2 Display Driver
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Windows CE 3.x Display Drivers
Document Number: X23A-E-006-01
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WINDOWS CE 3.x DISPLAY DRIVERS
Example Driver Builds
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Installation for CEPC Environment
Configuration
Compile Switches
Mode File
Resource Management Issues
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1.1 Features
2 Installation and Configuration
3 LCD Interface Pin Mapping
Table 3-1: LCD Signal Connector (J6)
4 CPU/Bus Interface Connector Pinouts
Table 4-1: CPU/BUS Connector (H1) Pinout
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5 Host Bus Interface Pin Mapping
6 Technical Description
6.1 ISA Bus Support
6.2 Non-ISA Bus Support
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6.8 Color TFT/D-TFD LCD Panel Support
6.9 CRT Support
6.10 Power Save Modes
6.11 Adjustable LCD Panel Negative Power Supply
6.12 Adjustable LCD Panel Positive Power Supply
6.13 CPU/Bus Interface Header Strips
6.14 Schematic Notes
7 Parts List
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8 Schematic Diagrams
Figure 1: S1D13505B00C Schematic Diagram (1 of 4)
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Figure 2: S1D13505B00C Schematic Diagram (2 of 4)
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Figure 3: S1D13505B00C Schematic Diagram (3 of 4)
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Figure 4: S1D13505B00C Schematic Diagram (4 of 4)
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S5U13505-D9000
Evaluation Board User Manual
Document Number: X23A-G-002-04
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2 Features
2.1 S1D13505 Embedded RAMDAC LCD/CRT Controller
2.1.1 Display Buffer
2.1.2 LCD Display Support
Table 2-1: LCD Connector Pinout
2.1.3 Touchscreen Support
2.1.4 CRT Support
2.1.5 Jumper Selection
2.1.6 Adjustable LCD BIAS Power Supply
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3 D9000 Specifics
3.1 Interface Signals
3.1.1 Connector Pinout for Channel A6 and A7
Table 3-1: Connectors Pinout for Channel A7
Table 3-1: Connectors Pinout for Channel A7 (Continued)
Table 3-2: Connectors Pinout for Channel A6
Table 3-2: Connectors Pinout for Channel A6 (Continued)
3.1.2 Memory Address (CS#, M/R#) Decoding
3.2 FPGA Code Functionality
3.3 Board Dimensions
4 Parts List
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Evaluation Board User Manual S5U13505-D9000 Issue Date: 01/02/05 X23A-G-002-04
5 Schematic Diagrams
Figure 5-1: S5U13505-D9000 Schematic Diagram (1 of 3)
Page 20 Epson Research and Development
S5U13505-D9000 Evaluation Board User Manual X23A-G-002-04 Issue Date: 01/02/05
Figure 5-2: S5U13505-D9000 Schematic Diagram (2 of 3)
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Evaluation Board User Manual S5U13505-D9000 Issue Date: 01/02/05 X23A-G-002-04
Figure 5-3: S5U13505-D9000 Schematic Diagram (3 of 3)
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1 S1D13505 Power Consumption
1.1 Conditions
2 Summary
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2 Interfacing to the PR31500/PR31700
3.1 PR31500/PR31700 Host Bus Interface Pin Mapping
3.2 PR31500/PR31700 Host Bus Interface Signals
4 Direct Connection to the Philips PR31500/PR31700
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4.3 Memory Mapping and Aliasing
5 System Design Using the IT8368E PC Card Buffer
5.1 Hardware Description
5.2 IT8368E Configuration
5.3 S1D13505 Configuration
6 Software
7 References
7.1 Documents
7.2 Document Sources
8 Technical Support
8.1 EPSON LCD/CRT Controllers (S1D13505)
8.3 ITE IT8368E
8.2 Philips MIPS PR31500/PR31700 Processor
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2 Interfacing to the PC Card Bus
2.1 The PC Card System Bus
2.1.1 PC Card Overview
2.1.2 Memory Access Cycles
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Figure 2-2: illustrates a typical memory access write cycle on the PC Card bus.
Figure 2-2: PC Card Write Cycle
3.1 PC Card Host Bus Interface Pin Mapping
3.2 PC Card Host Bus Interface Signals
4 PC Card to S1D13505 Interface
The following diagram shows a typical implementation of the PC Card to S1D13505 interface.
Figure 4-1: Typical Implementation of PC Card to S1D13505 Interface
4.3 Performance
4.4 Register/Memory Mapping
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7.2 PC Card Standard
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2 Interfacing to the VR4102/VR4111
2.1 The NEC VR4102/VR4111 System Bus
2.1.2 LCD Memory Access Cycles
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3.2 Host Bus Interface Signals Descriptions
4 VR4102/VR4111 to S1D13505 Interface
Figure 4-1: NEC VR4102/VR4111 to S1D13505 Configuration Schematic
4.3 NEC VR4102/VR4111 Configuration
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7.2 NEC Electronics Inc. (VR4102/VR4111).
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2 Interfacing to the MPC821
2.1 The MPC8xx System Bus
2.2 MPC821 Bus Overview
2.2.1 Normal (Non-Burst) Bus Transactions
2.2.2 Burst Cycles
2.3 Memory Controller Module
2.3.1 General-Purpose Chip Select Module (GPCM)
2.3.2 User-Programmable Machine (UPM)
3.1 PowerPC Host Bus Interface Pin Mapping
3.2 PowerPC Host Bus Interface Signals
4 MPC821 to S1D13505 Interface
4.2 Hardware Connections
Table 4-1: List of Connections from MPC821ADS to S1D13505 (Continued)
4.3 S1D13505 Hardware Configuration
4.4 Register/Memory Mapping
4.5 MPC821 Chip Select Configuration
4.6 Test Software
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7.2 Motorola MPC821 Processor
Motorola Design Line, (800) 521-6274. Local Motorola sales office or authorized di stributor.
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2 Interfacing to the TX3912
3.1 TX3912 Host Bus Interface Pin Mapping
3.2 TX3912 Host Bus Interface Signals
4 Direct Connection to the Toshiba TX3912
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4.3 Memory Mapping and Aliasing
5 System Design Using the IT8368E PC Card Buffer
5.1 Hardware Description
5.2 IT8368E Configuration
5.3 S1D13505 Configuration
6 Software
7 References
7.1 Documents
7.2 Document Sources
8 Technical Support
8.1 EPSON LCD/CRT Controllers (S1D13505)
8.2 Toshiba MIPS TX3912 Processor 8.3 ITE IT8368E
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2 Interfacing to the NEC VR4121
2.1 The NEC VR4121 System Bus
2.1.2 LCD Memory Access Cycles
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3.2 Host Bus Interface Signal Descriptions
4 VR4121 to S1D13505 Interface
Figure 4-1: NEC VR4121 to S1D13505 Configuration Schematic
4.3 NEC VR4121 Configuration
4.4 Memory Mapping and Aliasing
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7.2 NEC Electronics Inc. (VR4121).
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2 Interfacing to the NEC V832
2.1 The NEC V832 System Bus
2.1.2 Access Cycles
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3.2 Host Bus Interface Signal Descriptions
4 V832 to S1D13505 Interface
Note:
Figure 4-1: NEC V832 to S1D13505 Configuration Schematic
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4.3 NEC V832 Configuration
4.4 Memory Mapping and Aliasing
Table 4-3: NEC V832 IO Address Range For Each CSn Line
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7.2 NEC Electronics Inc. (V832).
