Samsung S3C9228/P9228 manuals

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Samsung S3C9228/P9228 User Manual

Samsung S3C9228/P9228 User Manual

462 pages938.12 Kb

3Important Notice
4Preface
6Table of Contents
- Part I Programming Model
  - Chapter 1 Product Overview
  - Chapter 2 Address Spaces
  - Chapter 3 Addressing Modes
  - 7Chapter 4 Control Registers
  - Chapter 5 Interrupt Structure
  - Chapter 6 SAM88RCRI Instruction Set
- 8Part II Hardware Descriptions
  - Chapter 7 Clock Circuit
  - Chapter 8 RESETRESET and Power-Down
  - Chapter 9 I/O Ports
  - Chapter 10 Basic Timer
  - 9Chapter 11 Timer 1
  - Chapter 12 Watch Timer
  - Chapter 13LCD Controller/Driver
  - Chapter 1410-Bit A/D Converter
  - Chapter 15Serial I/O Interface
10Table of Contents
12List of Figures
15List of Figures
16List of Tables
18List of Programming Tips
20List of Register Descriptions
22List of Instruction Descriptions
231
- SAM88RCRI PRODUCT FAMILY
- S3C9228/P9228 MICROCONTROLLER
- OTP
- 24FEATURES
  - 25Figure 1-1. Block Diagram
    - 1-3
- 26PIN ASSIGNMENTS
  - Figure 1-2. S3C9228 44-QFP Pin Assignments
  - 27Figure 1-3. S3C9228 42-SDIP Pin Assignments
    - 1-5
- 28PIN DESCRIPTIONS
- 30PIN CIRCUIT DIAGRAMS
  - Figure 1-4. Pin Circuit Type B
  - Figure 1-5. Pin Circuit Type C
  - 31Figure 1-7. Pin Circuit Type E-4
  - Figure 1-8. Pin Circuit Type F-16A
  - 32Figure 1-9. Pin Circuit Type H-23
  - 33Figure 1-10. Pin Circuit Type H-32
  - Figure 1-11. Pin Circuit Type H-32A
  - 34Figure 1-12. Pin Circuit Type H-32B
352
- 36PROGRAM MEMORY (ROM)
  - Figure 2-1. S3C9228/P9228 Program Memory Address Space
- 37REGISTER ARCHITECTURE
- COMMON WORKING REGISTER AREA (C0HCFH)
- 38++ PROGRAMMING TIP Addressing the Common Working Register Area
  - 39SYSTEM STACK
- 40+ +
413
- 42Figure 3-1. Register Addressing
- Figure 3-2. Working Register Addressing
- 44Figure 3-4. Indirect Register Addressing to Program Memory
- 45Figure 3-5. Indirect Working Register Addressing to Register File
- 46INDIRECT REGISTER ADDRESSING MODE (Concluded)
- Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
- 48INDEXED ADDRESSING MODE (Continued)
- Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
- 49INDEXED ADDRESSING MODE (Concluded)
- Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
- 51DIRECT ADDRESS MODE (Continued)
- Figure 3-11. Direct Addressing for Call and Jump Instructions
534
- 56FLAGS
  - Bit Identifier RESET RESET Value Read/Write
  - Figure 4-1. Register Description Format
- 57ADCON A/D Converter Control Register D0H
- 58BTCON Basic Timer Control Register DCH
- 59CLKCON
- 60FLAGS
- 61INTPND1 Interrupt Pending Register 1 D6H
- 62INTPND2 Interrupt Pending Register 2 D7H
- 63LMOD
- 64LPOT
- 65OSCCON
- 66P0CON
- 67P0INT
- 68P0PUR
- 69P0EDGE
- 70P1CON
- 71P1INT
- 72P1PUR
- 73P1EDGE
- 74P2CON
- 75P2PUR
- 76P3CON
- 77P3INT
- 78P3PUR
- 79P3EDGE
- 80P4CONH
- 81P4CONL
- 82P5CONH
- 83P5CONL
- 84P6CON
- 85SIOCON SIO Control Register E1H
- 86STPCON
- 87SYM
- 88T A CON
- 89T B CON
- 90WTCON
915
- 95Figure 5-3. S3C9228/P9228 Interrupt Structure
976
1477
- S3C9228/P9228 CLOCK CIRCUITS
- 7-3
- 149Figure 7-6. System Clock Circuit Diagram
- 153+ +
1558
- SYSTEM RESET
- 156POWER-DOWN MODES
1619
- 164Figure 9-2. Port 0 Control Register (P0CON)
- Figure 9-3. Port 0 Interrupt Control Register (P0INT)
- 165Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)
- Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)
- Figure 9-6. Port 0 Pull-up Control Register (P0PUR)
- 167Figure 9-8. Port 1 Interrupt Control Register (P1INT)
- Figure 9-9. Port 1 Interrupt Pending Bits (INTPND1.7-.4)
- 168Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE)
- Figure 9-11. Port 1 Pull-up Control Register (P1PUR)
- 170Figure 9-13. Port 2 Pull-up Control Register (P2PUR)
- 172Figure 9-15. Port 3 Interrupt Control Register (P3INT)
- Figure 9-16. Port 3 Interrupt Pending Bits (INTPND2.5-.4)
- 173Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE)
- Figure 9-18. Port 3 Pull-up Control Register (P3PUR)
17710
- 180Figure 10-2. Basic Timer Block Diagram
18111
- ONE 16-BIT TIMER MODE (TIMER 1)
  - 183Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)
    - 11-3
- 184TWO 8-BIT TIMERS MODE (TIMER A and B)
  - 186Figure 11-4. Timer B Control Register (TBCON)
    - TIMER 1 S3C9228/P9228
  - 188Figure 11-5. Timer A Block Diagram(Two 8-bit Timers Mode)
    - 11-8
  - 189Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)
    - 11-9
19112
- 193WATCH TIMER CIRCUIT DIAGRAM
  - Figure 12-2. Watch Timer Circuit Diagram
19513
- 196LCD CIRCUIT DIAGRAM
- Figure 13-2. LCD Circuit Diagram
- 199Figure 13-5. LCD Port Control Register
- 200LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias
- 1/4 Bias
- 1/3 Bias
- 201Figure 13-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
  - LCD CONTROLLER/DRIVER S3C9228/P9228
- 202Figure 13-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
  - 13-8
- 203Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
20514
- FUNCTION DESCRIPTION
  - 207Figure 14-3. A/D Converter Functional Block Diagram
20915
- Figure 15-2. SIO Prescaler Register (SIOPS)
- Figure 15-3. SIO Functional Block Diagram
- 211SIO BLOCK DIAGRAM
  - 212SERIAL I/O TIMING DIAGRAM (SIO)
  - Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
  - Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
21316
- 221Figure 16-4. Input Timing for RESETRESET
- Figure 16-5. Serial Data Transfer Timing
- 225
- Figure 16-8. Operating Voltage Range
22717
- The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package.
- Figure 17-1. 42-SDIP-600 Package Dimensions
- 42-SDIP-600
- 22844-QFP-1010B
  - Figure 17-2. 44-QFP-1010B Package Dimensions
22918
- Figure 18-1. S3P9228 44-QFP Pin Assignments
- S3C9228
  - S3P9228 OTP S3C9228/P9228
  - 230Figure 18-2. S3P9228 42-SDIP Pin Assignments
    - 18-2
  - 233Figure 18-3. Standard Operating Voltage Range
23519
- 236Figure 19-1. SMDS Product Configuration (SMDS2+)
- 237TB9228
  - Figure 19-2. TB9228 Target Board Configuration
  - SM1347A
    - 240Figure 19-3. Connectors (J101, J102) for TB9228
    - 241
    - Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package
    - Figure 19-5. S3C9228 Probe Adapter for 44-QFP Package
2431
- SAM88RCRI PRODUCT FAMILY
- S3C9228/P9228 MICROCONTROLLER
- OTP
- 244FEATURES
  - 245Figure 1-1. Block Diagram
    - 1-3
- 246PIN ASSIGNMENTS
  - Figure 1-2. S3C9228 44-QFP Pin Assignments
  - 247Figure 1-3. S3C9228 42-SDIP Pin Assignments
    - 1-5
- 248PIN DESCRIPTIONS
- 250PIN CIRCUIT DIAGRAMS
  - Figure 1-4. Pin Circuit Type B
  - Figure 1-5. Pin Circuit Type C
  - 251Figure 1-7. Pin Circuit Type E-4
  - Figure 1-8. Pin Circuit Type F-16A
  - 252Figure 1-9. Pin Circuit Type H-23
  - 253Figure 1-10. Pin Circuit Type H-32
  - Figure 1-11. Pin Circuit Type H-32A
  - 254Figure 1-12. Pin Circuit Type H-32B
2552
- 256PROGRAM MEMORY (ROM)
  - Figure 2-1. S3C9228/P9228 Program Memory Address Space
- 257REGISTER ARCHITECTURE
- COMMON WORKING REGISTER AREA (C0HCFH)
- 258++ PROGRAMMING TIP Addressing the Common Working Register Area
  - 259SYSTEM STACK
- 260+ +
2613
- 262Figure 3-1. Register Addressing
- Figure 3-2. Working Register Addressing
- 264Figure 3-4. Indirect Register Addressing to Program Memory
- 265Figure 3-5. Indirect Working Register Addressing to Register File
- 266INDIRECT REGISTER ADDRESSING MODE (Concluded)
- Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
- 268INDEXED ADDRESSING MODE (Continued)
- Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
- 269INDEXED ADDRESSING MODE (Concluded)
- Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
- 271DIRECT ADDRESS MODE (Continued)
- Figure 3-11. Direct Addressing for Call and Jump Instructions
2734
- 276FLAGS
  - Bit Identifier RESET RESET Value Read/Write
  - Figure 4-1. Register Description Format
- 277ADCON A/D Converter Control Register D0H
- 278BTCON Basic Timer Control Register DCH
- 279CLKCON
- 280FLAGS
- 281INTPND1 Interrupt Pending Register 1 D6H
- 282INTPND2 Interrupt Pending Register 2 D7H
- 283LMOD
- 284LPOT
- 285OSCCON
- 286P0CON
- 287P0INT
- 288P0PUR
- 289P0EDGE
- 290P1CON
- 291P1INT
- 292P1PUR
- 293P1EDGE
- 294P2CON
- 295P2PUR
- 296P3CON
- 297P3INT
- 298P3PUR
- 299P3EDGE
- 300P4CONH
- 301P4CONL
- 302P5CONH
- 303P5CONL
- 304P6CON
- 305SIOCON SIO Control Register E1H
- 306STPCON
- 307SYM
- 308T A CON
- 309T B CON
- 310WTCON
3115
- 315Figure 5-3. S3C9228/P9228 Interrupt Structure
3176
3677
- S3C9228/P9228 CLOCK CIRCUITS
- 7-3
- 369Figure 7-6. System Clock Circuit Diagram
- 373+ +
3758
- SYSTEM RESET
- 376POWER-DOWN MODES
3819
- 384Figure 9-2. Port 0 Control Register (P0CON)
- Figure 9-3. Port 0 Interrupt Control Register (P0INT)
- 385Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)
- Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)
- Figure 9-6. Port 0 Pull-up Control Register (P0PUR)
- 387Figure 9-8. Port 1 Interrupt Control Register (P1INT)
- Figure 9-9. Port 1 Interrupt Pending Bits (INTPND1.7-.4)
- 388Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE)
- Figure 9-11. Port 1 Pull-up Control Register (P1PUR)
- 390Figure 9-13. Port 2 Pull-up Control Register (P2PUR)
- 392Figure 9-15. Port 3 Interrupt Control Register (P3INT)
- Figure 9-16. Port 3 Interrupt Pending Bits (INTPND2.5-.4)
- 393Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE)
- Figure 9-18. Port 3 Pull-up Control Register (P3PUR)
39710
- 400Figure 10-2. Basic Timer Block Diagram
40111
- ONE 16-BIT TIMER MODE (TIMER 1)
  - 403Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)
    - 11-3
- 404TWO 8-BIT TIMERS MODE (TIMER A and B)
  - 406Figure 11-4. Timer B Control Register (TBCON)
    - TIMER 1 S3C9228/P9228
  - 408Figure 11-5. Timer A Block Diagram(Two 8-bit Timers Mode)
    - 11-8
  - 409Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)
    - 11-9
41112
- 413WATCH TIMER CIRCUIT DIAGRAM
  - Figure 12-2. Watch Timer Circuit Diagram
41513
- 416LCD CIRCUIT DIAGRAM
- Figure 13-2. LCD Circuit Diagram
- 419Figure 13-5. LCD Port Control Register
- 420LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias
- 1/4 Bias
- 1/3 Bias
- 421Figure 13-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
  - LCD CONTROLLER/DRIVER S3C9228/P9228
- 422Figure 13-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
  - 13-8
- 423Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
42514
- FUNCTION DESCRIPTION
  - 427Figure 14-3. A/D Converter Functional Block Diagram
42915
- Figure 15-2. SIO Prescaler Register (SIOPS)
- Figure 15-3. SIO Functional Block Diagram
- 431SIO BLOCK DIAGRAM
  - 432SERIAL I/O TIMING DIAGRAM (SIO)
  - Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
  - Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
43316
- 441Figure 16-4. Input Timing for RESETRESET
- Figure 16-5. Serial Data Transfer Timing
- 445
- Figure 16-8. Operating Voltage Range
44717
- The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package.
- Figure 17-1. 42-SDIP-600 Package Dimensions
- 42-SDIP-600
- 44844-QFP-1010B
  - Figure 17-2. 44-QFP-1010B Package Dimensions
44918
- Figure 18-1. S3P9228 44-QFP Pin Assignments
- S3C9228
  - S3P9228 OTP S3C9228/P9228
  - 450Figure 18-2. S3P9228 42-SDIP Pin Assignments
    - 18-2
  - 453Figure 18-3. Standard Operating Voltage Range
45519
- 456Figure 19-1. SMDS Product Configuration (SMDS2+)
- 457TB9228
  - Figure 19-2. TB9228 Target Board Configuration
  - SM1347A
    - 460Figure 19-3. Connectors (J101, J102) for TB9228
    - 461
    - Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package
    - Figure 19-5. S3C9228 Probe Adapter for 44-QFP Package

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