Samsung 8-Bit CMOS Microcontroller, S3C9228/P9228 Port 0 Interrupt Pending Bits INTPND1.3-.0

S3C9228/P9228 I/O PORTS

Port 0 Interrupt Pending Bits (INTPND1.3-.0)

D6H, Page 0, R/W

MSB .7 .6 .5 .4 .3 .2 .1 .0

P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT)

LSB

INTPND1 bit configuration settings:

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)

Port 0 Interrupt Edge Selection Register (P0EDGE)

EEH, Page 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used	P0.3	P0.2	P0.1	P0.0
	(INT)	(INT)	(INT)	(INT)

P0EDGE bit configuration settings:

0Falling edge detection

1Rising edge detection

Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)

Port 0 Pull-up Control Register (P0PUR)

ECH, Page 0, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used P0.3 P0.2 P0.1 P0.0

P0PUR bit configuration settings:

0Disable pull-up resistor

1Enable pull-up resistor

Figure 9-6. Port 0 Pull-up Control Register (P0PUR)

9-5