Main
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Important Notice
Preface
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Table of Contents
Part I Programming Model
Chapter 1 Product Overview
Chapter 2 Address Spaces
Chapter 3 Addressing Modes
Chapter 4 Control Registers
Chapter 5 Interrupt Structure
Chapter 6 SAM88RCRI Instruction Set
Part II Hardware Descriptions
Chapter 7 Clock Circuit
Chapter 8 RESETRESET and Power-Down
Chapter 9 I/O Ports
Chapter 10 Basic Timer
Chapter 11 Timer 1
Chapter 12 Watch Timer
Chapter 13LCD Controller/Driver
Chapter 1410-Bit A/D Converter
Chapter 15Serial I/O Interface
Table of Contents
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List of Figures
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List of Figures
List of Tables
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List of Programming Tips
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List of Register Descriptions
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List of Instruction Descriptions
1
SAM88RCRI PRODUCT FAMILY
S3C9228/P9228 MICROCONTROLLER
OTP
FEATURES
Figure 1-1. Block Diagram
1-3
PIN ASSIGNMENTS
Figure 1-2. S3C9228 44-QFP Pin Assignments
Figure 1-3. S3C9228 42-SDIP Pin Assignments
1-5
PIN DESCRIPTIONS
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PIN CIRCUIT DIAGRAMS
Figure 1-4. Pin Circuit Type B
Figure 1-5. Pin Circuit Type C
Figure 1-7. Pin Circuit Type E-4
Figure 1-8. Pin Circuit Type F-16A
Figure 1-9. Pin Circuit Type H-23
Figure 1-10. Pin Circuit Type H-32
Figure 1-11. Pin Circuit Type H-32A
Figure 1-12. Pin Circuit Type H-32B
2
PROGRAM MEMORY (ROM)
Figure 2-1. S3C9228/P9228 Program Memory Address Space
REGISTER ARCHITECTURE
COMMON WORKING REGISTER AREA (C0HCFH)
++ PROGRAMMING TIP Addressing the Common Working Register Area
SYSTEM STACK
+ +
3
Figure 3-1. Register Addressing
Figure 3-2. Working Register Addressing
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Figure 3-4. Indirect Register Addressing to Program Memory
Figure 3-5. Indirect Working Register Addressing to Register File
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
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INDEXED ADDRESSING MODE (Continued)
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
INDEXED ADDRESSING MODE (Concluded)
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
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DIRECT ADDRESS MODE (Continued)
Figure 3-11. Direct Addressing for Call and Jump Instructions
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4
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FLAGS
Bit Identifier RESET RESET Value Read/Write
Figure 4-1. Register Description Format
ADCON A/D Converter Control Register D0H
BTCON Basic Timer Control Register DCH
CLKCON
FLAGS
INTPND1 Interrupt Pending Register 1 D6H
INTPND2 Interrupt Pending Register 2 D7H
LMOD
LPOT
OSCCON
P0CON
P0INT
P0PUR
P0EDGE
P1CON
P1INT
P1PUR
P1EDGE
P2CON
P2PUR
P3CON
P3INT
P3PUR
P3EDGE
P4CONH
P4CONL
P5CONH
P5CONL
P6CON
SIOCON SIO Control Register E1H
STPCON
SYM
T A CON
T B CON
WTCON
5
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Figure 5-3. S3C9228/P9228 Interrupt Structure
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ADC Add With Carry
ADD Add
AND Logical AND
CALL Call Procedure
CCF Complement Carry Flag
CLR Clear
COM Complement
CP Compare
DEC Decrement
DI Disable Interrupts
EI Enable Interrupts
IDLE Idle Operation
INC Increment
IRET Interrupt Return
JP Jump
JR Jump Relative
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LDCD/LDED Load Memory and Decrement
LDCI/LDEI Load Memory and Increment
NOP No Operation
OR Logical OR
POP Pop From Stack
PUSH Push To Stack
RCF Reset Carry Flag
RET Return
RL Rotate Left
RLC Rotate Left Through Carry
RR Rotate Right
RRC Rotate Right Through Carry
SBC Subtract With Carry
SCF Set Carry Flag
SRA Shift Right Arithmetic
STOP Stop Operation
SUB Subtract
TCM Test Complement Under Mask
TM Test Under Mask
XOR
7
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S3C9228/P9228 CLOCK CIRCUITS
7-3
Figure 7-6. System Clock Circuit Diagram
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+ +
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8
SYSTEM RESET
POWER-DOWN MODES
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9
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Figure 9-2. Port 0 Control Register (P0CON)
Figure 9-3. Port 0 Interrupt Control Register (P0INT)
Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)
Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)
Figure 9-6. Port 0 Pull-up Control Register (P0PUR)
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Figure 9-8. Port 1 Interrupt Control Register (P1INT)
Figure 9-9. Port 1 Interrupt Pending Bits (INTPND1.7-.4)
Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE)
Figure 9-11. Port 1 Pull-up Control Register (P1PUR)
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Figure 9-13. Port 2 Pull-up Control Register (P2PUR)
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Figure 9-15. Port 3 Interrupt Control Register (P3INT)
Figure 9-16. Port 3 Interrupt Pending Bits (INTPND2.5-.4)
Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE)
Figure 9-18. Port 3 Pull-up Control Register (P3PUR)
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10
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Figure 10-2. Basic Timer Block Diagram
11
ONE 16-BIT TIMER MODE (TIMER 1)
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Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)
11-3
TWO 8-BIT TIMERS MODE (TIMER A and B)
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Figure 11-4. Timer B Control Register (TBCON)
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TIMER 1 S3C9228/P9228
Figure 11-5. Timer A Block Diagram(Two 8-bit Timers Mode)
11-8
Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)
11-9
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12
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WATCH TIMER CIRCUIT DIAGRAM
Figure 12-2. Watch Timer Circuit Diagram
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13
LCD CIRCUIT DIAGRAM
Figure 13-2. LCD Circuit Diagram
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Figure 13-5. LCD Port Control Register
LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias
1/4 Bias
1/3 Bias
Figure 13-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
LCD CONTROLLER/DRIVER S3C9228/P9228
Figure 13-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
13-8
Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
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FUNCTION DESCRIPTION
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Figure 14-3. A/D Converter Functional Block Diagram
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Figure 15-2. SIO Prescaler Register (SIOPS)
Figure 15-3. SIO Functional Block Diagram
SIO BLOCK DIAGRAM
SERIAL I/O TIMING DIAGRAM (SIO)
Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
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Figure 16-4. Input Timing for RESETRESET
Figure 16-5. Serial Data Transfer Timing
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Figure 16-8. Operating Voltage Range
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The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package.
Figure 17-1. 42-SDIP-600 Package Dimensions
42-SDIP-600
44-QFP-1010B
Figure 17-2. 44-QFP-1010B Package Dimensions
18
Figure 18-1. S3P9228 44-QFP Pin Assignments
S3C9228
S3P9228 OTP S3C9228/P9228
Figure 18-2. S3P9228 42-SDIP Pin Assignments
18-2
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Figure 18-3. Standard Operating Voltage Range
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19
Figure 19-1. SMDS Product Configuration (SMDS2+)
TB9228
Figure 19-2. TB9228 Target Board Configuration
SM1347A
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Figure 19-3. Connectors (J101, J102) for TB9228
Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package
Figure 19-5. S3C9228 Probe Adapter for 44-QFP Package
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1
SAM88RCRI PRODUCT FAMILY
S3C9228/P9228 MICROCONTROLLER
OTP
FEATURES
Figure 1-1. Block Diagram
1-3
PIN ASSIGNMENTS
Figure 1-2. S3C9228 44-QFP Pin Assignments
Figure 1-3. S3C9228 42-SDIP Pin Assignments
1-5
PIN DESCRIPTIONS
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PIN CIRCUIT DIAGRAMS
Figure 1-4. Pin Circuit Type B
Figure 1-5. Pin Circuit Type C
Figure 1-7. Pin Circuit Type E-4
Figure 1-8. Pin Circuit Type F-16A
Figure 1-9. Pin Circuit Type H-23
Figure 1-10. Pin Circuit Type H-32
Figure 1-11. Pin Circuit Type H-32A
Figure 1-12. Pin Circuit Type H-32B
2
PROGRAM MEMORY (ROM)
Figure 2-1. S3C9228/P9228 Program Memory Address Space
REGISTER ARCHITECTURE
COMMON WORKING REGISTER AREA (C0HCFH)
++ PROGRAMMING TIP Addressing the Common Working Register Area
SYSTEM STACK
+ +
3
Figure 3-1. Register Addressing
Figure 3-2. Working Register Addressing
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Figure 3-4. Indirect Register Addressing to Program Memory
Figure 3-5. Indirect Working Register Addressing to Register File
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
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INDEXED ADDRESSING MODE (Continued)
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
INDEXED ADDRESSING MODE (Concluded)
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
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DIRECT ADDRESS MODE (Continued)
Figure 3-11. Direct Addressing for Call and Jump Instructions
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4
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FLAGS
Bit Identifier RESET RESET Value Read/Write
Figure 4-1. Register Description Format
ADCON A/D Converter Control Register D0H
BTCON Basic Timer Control Register DCH
CLKCON
FLAGS
INTPND1 Interrupt Pending Register 1 D6H
INTPND2 Interrupt Pending Register 2 D7H
LMOD
LPOT
OSCCON
P0CON
P0INT
P0PUR
P0EDGE
P1CON
P1INT
P1PUR
P1EDGE
P2CON
P2PUR
P3CON
P3INT
P3PUR
P3EDGE
P4CONH
P4CONL
P5CONH
P5CONL
P6CON
SIOCON SIO Control Register E1H
STPCON
SYM
T A CON
T B CON
WTCON
5
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Figure 5-3. S3C9228/P9228 Interrupt Structure
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ADC Add With Carry
ADD Add
AND Logical AND
CALL Call Procedure
CCF Complement Carry Flag
CLR Clear
COM Complement
CP Compare
DEC Decrement
DI Disable Interrupts
EI Enable Interrupts
IDLE Idle Operation
INC Increment
IRET Interrupt Return
JP Jump
JR Jump Relative
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LDCD/LDED Load Memory and Decrement
LDCI/LDEI Load Memory and Increment
NOP No Operation
OR Logical OR
POP Pop From Stack
PUSH Push To Stack
RCF Reset Carry Flag
RET Return
RL Rotate Left
RLC Rotate Left Through Carry
RR Rotate Right
RRC Rotate Right Through Carry
SBC Subtract With Carry
SCF Set Carry Flag
SRA Shift Right Arithmetic
STOP Stop Operation
SUB Subtract
TCM Test Complement Under Mask
TM Test Under Mask
XOR
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S3C9228/P9228 CLOCK CIRCUITS
7-3
Figure 7-6. System Clock Circuit Diagram
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+ +
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8
SYSTEM RESET
POWER-DOWN MODES
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9
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Figure 9-2. Port 0 Control Register (P0CON)
Figure 9-3. Port 0 Interrupt Control Register (P0INT)
Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)
Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)
Figure 9-6. Port 0 Pull-up Control Register (P0PUR)
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Figure 9-8. Port 1 Interrupt Control Register (P1INT)
Figure 9-9. Port 1 Interrupt Pending Bits (INTPND1.7-.4)
Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE)
Figure 9-11. Port 1 Pull-up Control Register (P1PUR)
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Figure 9-13. Port 2 Pull-up Control Register (P2PUR)
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Figure 9-15. Port 3 Interrupt Control Register (P3INT)
Figure 9-16. Port 3 Interrupt Pending Bits (INTPND2.5-.4)
Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE)
Figure 9-18. Port 3 Pull-up Control Register (P3PUR)
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Figure 10-2. Basic Timer Block Diagram
11
ONE 16-BIT TIMER MODE (TIMER 1)
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Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)
11-3
TWO 8-BIT TIMERS MODE (TIMER A and B)
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Figure 11-4. Timer B Control Register (TBCON)
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TIMER 1 S3C9228/P9228
Figure 11-5. Timer A Block Diagram(Two 8-bit Timers Mode)
11-8
Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)
11-9
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WATCH TIMER CIRCUIT DIAGRAM
Figure 12-2. Watch Timer Circuit Diagram
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13
LCD CIRCUIT DIAGRAM
Figure 13-2. LCD Circuit Diagram
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Figure 13-5. LCD Port Control Register
LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias
1/4 Bias
1/3 Bias
Figure 13-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
LCD CONTROLLER/DRIVER S3C9228/P9228
Figure 13-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
13-8
Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
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FUNCTION DESCRIPTION
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Figure 14-3. A/D Converter Functional Block Diagram
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Figure 15-2. SIO Prescaler Register (SIOPS)
Figure 15-3. SIO Functional Block Diagram
SIO BLOCK DIAGRAM
SERIAL I/O TIMING DIAGRAM (SIO)
Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
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Figure 16-4. Input Timing for RESETRESET
Figure 16-5. Serial Data Transfer Timing
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Figure 16-8. Operating Voltage Range
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The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package.
Figure 17-1. 42-SDIP-600 Package Dimensions
42-SDIP-600
44-QFP-1010B
Figure 17-2. 44-QFP-1010B Package Dimensions
18
Figure 18-1. S3P9228 44-QFP Pin Assignments
S3C9228
S3P9228 OTP S3C9228/P9228
Figure 18-2. S3P9228 42-SDIP Pin Assignments
18-2
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Figure 18-3. Standard Operating Voltage Range
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Figure 19-1. SMDS Product Configuration (SMDS2+)
TB9228
Figure 19-2. TB9228 Target Board Configuration
SM1347A
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Figure 19-3. Connectors (J101, J102) for TB9228
Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package
Figure 19-5. S3C9228 Probe Adapter for 44-QFP Package