Samsung S3C9228/P9228, 8-Bit CMOS Microcontroller user manual TA = 25 C, VDD = 0

ELECTRICAL DATA				S3C9228/P9228
			RESET	Oscillation
			Occurs	Stabilization
				TIme
	~~	Stop Mode
		Data Retention Mode		Normal
	~~			Operating Mode
VDD
		VDDDR
	Execution of
	STOP Instrction
RESET				0.8 VDD
			0.2 VDD	tWAIT
	NOTE:	tWAIT is the same as 16	× 1/BT clock.

Figure 16-2. Stop Mode Release Timing When Initiated by a RESET

Table 16-4. Input/Output Capacitance

(TA = 25 °C, VDD = 0 V)

Parameter	Symbol	Conditions	Min	Typ	Max	Unit
Input	CIN	f = 1 MHz; unmeasured pins	–	–	10	pF
capacitance		are connected to VSS
Output	COUT
capacitance
I/O capacitance	CIO

16-6