Samsung S3C9228/P9228, 8-Bit CMOS Microcontroller user manual Basic Timer Block Diagram

BASIC TIMER S3C9228/P9228 (Preliminary Spec)

fXX/4096

fXX/1024

Bits 3, 2

RESET or STOP Bit 1

Data Bus

Clear

Basic Timer Control Register (Write '1010xxxxB' to Disable)

fXX

DIV

R

Bit 0

fXX/128

fXX/16

MUX

8-Bit Up Counter	OVF	RESET
(BTCNT, Read-Only)

Start the CPU (note)

NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).

Figure 10-2. Basic Timer Block Diagram

10-4