Samsung 8-Bit CMOS Microcontroller, S3C9228/P9228 user manual Clock Status During POWER-DOWN Modes

S3C9228/P9228 CLOCK CIRCUITS

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

—In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When the fx is selected as system clock).

—In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt structure, timer A/B, and watch timer. Idle mode is released by a reset or by an external or internal interrupts.

INT		Stop Release
Main-System	fX			fXT	Sub-system	Watch Timer
Oscillator					Oscillator
						LCD Controller
Circuit					Circuit
		Selector 1
			fXX
Stop
OSCCON.3
OSCCON.0						Stop
						OSCCON.2
		1/8-1/4096			Basic Timer
STOP OSC					Timer/Counters
inst.		Frequency			Watch Timer
STPCON		Dividing			LCD Controller
		Circuit
					SIO
	1/1	1/2	1/8	1/16	A/D Converter
CLKCON.4-.3		Selector 2
						CPU

Figure 7-6. System Clock Circuit Diagram

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