Texas Instruments DM648 DSP manuals

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Texas Instruments DM648 DSP Manual

Texas Instruments DM648 DSP Manual

47 pages413.15 Kb

3Contents
- Preface
6Read This First
- 1 Introduction 1.1 Purpose of the Peripheral 1.2 Features
- 1.3 Functional Block Diagram
- User's Guide
9DSP DDR2 Memory Controller
- 101.4 Industry Standard(s) Compliance Statement
  - Introduction
    - DSP DDR2 Memory Controller10 SPRUEK5A October 2007Submit Documentation Feedback
  - Figure 1. DDR2 Memory Controller Block Diagram
  - 12Figure 2. DDR2 Memory Controller Signals
  - Table 1. DDR2 Memory Controller Signal Descriptions
- 132.4 Protocol Description(s)
  - Table 3. Truth Table for DDR2 SDRAM Commands
  - 152.4.3 Activation (ACTV)
  - Figure 4. Refresh Command
  - incurred. Figure 5. ACTV Command
  - 162.4.4 Deactivation (DCAB and DEAC)
- 182.5 Memory Width and Byte Alignment
- 192.6 Address Mapping
  - www.ti.com
  - 20Figure 12. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM
    - DSP DDR2 Memory Controller20 SPRUEK5A October 2007Submit Documentation Feedback
- 222.7 DDR2 Memory Controller Interface
  - Figure 14. DDR2 SDRAM Column, Row, and Bank Access
    - DSP DDR2 Memory Controller22 SPRUEK5A October 2007Submit Documentation Feedback
- 252.8 Refresh Scheduling
- 262.9 Self-Refresh Mode
- 2.10 Reset Considerations
- 272.11 DDR2 SDRAM Memory Initialization
- 282.12 Interrupt Support 2.13 EDMA Event Support 2.14 Emulation Considerations
- 333.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
  - 343.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)
  - Table 14. SDTIM1 Configuration
  - 353.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL)
  - Table 15. SDTIM2 Configuration
- 364 DDR2 Memory Controller Registers
- 374.1 Module ID and Revision Register (MIDR)
- 4.2 DDR2 Memory Controller Status Register (DMCSTAT)
  - Table 18. Module ID and Revision Register (MIDR) Field Descriptions
  - Table 19. DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions
- 384.3 SDRAM Configuration Register (SDCFG)
  - Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions
  - 39Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued)
- 404.4 SDRAM Refresh Control Register (SDRFC)
- 414.5 SDRAM Timing 1 Register (SDTIM1)
  - Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions
  - 42Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued)
- 434.6 SDRAM Timing 2 Register (SDTIM2)
  - Table 23. SDRAM Timing 2 Register (SDTIM2) Field Descriptions
- 444.7 Burst Priority Register (BPRIO)
  - Table 24. Burst Priority Register (BPRIO) Field Descriptions
- 454.8 DDR2 Memory Controller Control Register (DMCCTL)
  - Table 25. DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions
- 46Appendix A Revision History
  - Appendix A
  - 47IMPORTANT NOTICE

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