Protocol Descriptions | Texas Instruments DM648 DSP, TMS320DM647

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Peripheral Architecture

2.4Protocol Description(s)

The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 shows the signal truth table for the DDR2 SDRAM commands.

	Table 2. DDR2 SDRAM Commands
Command	Function
ACTV	Activates the selected bank and row.
DCAB	Precharge all command. Deactivates (precharges) all banks.
DEAC	Precharge single command. Deactivates (precharges) a single bank.
DESEL	Device Deselect.
EMRS	Extended Mode Register set. Allows altering the contents of the mode register.
MRS	Mode register set. Allows altering the contents of the mode register.
NOP	No operation.
Power Down	Power down mode.
READ	Inputs the starting column address and begins the read operation.
READ with	Inputs the starting column address and begins the read operation. The read operation is followed by a
autoprecharge	precharge.
REFR	Autorefresh cycle.
SLFREFR	Self-refresh mode.
WRT	Inputs the starting column address and begins the write operation.
WRT with	Inputs the starting column address and begins the write operation. The write operation is followed by a
autoprecharge	precharge.

Table 3. Truth Table for DDR2 SDRAM Commands

DDR2 SDRAM
Signals		CKE	CS	RAS	CAS	WE	BA[2:0]	A[13:11, 9:0]	A10
	DDR_CKE
DDR2 Memory	Previous						DDR_BA[2:0
Controller Signals	Cycles	Current Cycle	DDR_CS	DDR_RAS	DDR_CAS	DDR_WE	]	DDR_A[13:11, 9:0]	DDR_A[10]
ACTV	H(1)	H	L	L	H	H	Bank	Row Address
DCAB	H	H	L	L	H	L	X	X	L
DEAC	H	H	L	L	H	L	Bank	X	L
MRS	H	H	L	L	L	L	BA(2)	OP Code
EMRS	H	H	L	L	L	L	BA	OP Code
READ	H	H	L	H	L	H	BA	Column Address	L
READ with	H	H	L	H	L	H	BA	Column Address	H
precharge
WRT	H	H	L	H	L	L	BA	Column Address	L
WRT with precharge	H	H	L	H	L	L	BA	Column Address	L
REFR	H	H	L	L	L	H	X	X	X
SLFREFR	H	L	L	L	L	H	X	X	X
entry
SLFREFR	L	H	H	X	X	X	X	X	X
exit			L	H	H	H	X	X	X
			L	H	H	H	X	X	X
NOP	H	X	L	H	H	H	X	X	X
DESEL	H	X	H	X	X	X	X	X	X
Power Down entry	H	L	H	X	X	X	X	X	X
			L	H	H	H	X	X	X
Power Down exit	L	H	H	X	X	X	X	X	X
			L	H	H	H	X	X	X

(1)Legend: H means logic high; L means logic low; X means don'tcare (either H or L).

(2)BA refers to the bank address pins (BA[2:0]).

SPRUEK5A –October 2007

DSP DDR2 Memory Controller

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Texas Instruments DM648 DSP, TMS320DM647 Protocol Descriptions, Truth Table for DDR2 Sdram Commands, Command Function

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Mode Register Set MRS and EmrsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COL Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width and Byte Alignment Write WRT CommandAddressable Memory Ranges Memory Width Maximum Addressable Bytes Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Considerations Self-Refresh ModeReset Sources DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization 11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Function Selection Sdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration Dmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description Offset Acronym Register Description DDR2 Memory Controller Registers DDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Bit Field Value Description Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Tsxnr Tsxrd Trtp Tcke Burst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise Rese DDR2 Memory Controller Control Register Dmcctl Additions/Modifications/Deletions Table A-1. Document Revision History DSP Products ApplicationsRfid