Pin Description | Texas Instruments TMS320DM647, DM648 DSP specification

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Peripheral Architecture

Figure 2. DDR2 Memory Controller Signals

DDR_CLK

DDR_CLK

DDR_CKE

DDR_CS

DDR_WE

DDR_RAS

DDR2DDR_CAS memory

controller DDR_DQM[3:0] DDR_DQS[3:0]

DDR_DQS[3:0]

DDR_BA[2:0]

DDR_A[13:0]

DDR_D[31:0]

DDR_ODT[1:0]

DDR_DQGATE[3:0]

DDR_VREF

	Table 1. DDR2 Memory Controller Signal Descriptions
Pin	Description
DDR_D[31:0]	Bidirectional data bus. Input for data reads and output for data writes.
DDR_A[13:0]	External address output.
DDR_CS	Active-low chip enable for memory space CE0. DDR_CS is used to enable the DDR2 SDRAM memory
	device during external memory accesses. DDR_CS pin stays low throughout the operation of the DDR2
	memory controller; it never goes high. Note that this behavior does not affect the ability of the DDR2 memory
	controller to access DDR2 SDRAM memory devices.
DDR_DQM[3:0]	Active-low output data mask.
DDR_CLK/	Differential clock outputs.
DDR_CLK
DDR_CKE	Clock enable (used for self-refresh mode).
DDR_CAS	Active-low column address strobe.
DDR_RAS	Active-low row address strobe.
DDR_WE	Active-low write enable.
DDR_DQS[3:0]/	Differential data strobe bidirectional signals.
DDR_DQS[3:0]
DDR_ODT[1:0]	On-die termination signals to external DDR2 SDRAM. These pins are reserved for future use and should not
	be connected to the DDR2 SDRAM. Note: there are no on-die termination resistors implemented on the die
	of this device.
DDR_BA[2:0]	Bank-address control outputs.
DDR_DQGATE[3:0]	Data strobe gate pins. These pins are used as a timing reference during memory reads. The
	DDR_DQGATE0 and DDR_DQGATE2 pins should be routed out and connected to the DDR_DQGATE1 and
	DDR_DQGATE3 pins, respectively. For more routing requirements on these pins, see the device-specific
	data manual.
DDR_VREF	DDR2 Memory Controller reference voltage. This voltage must be supplied externally. See the
	device-specific data manual for more details.

12

DSP DDR2 Memory Controller

SPRUEK5A –October 2007

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Texas Instruments TMS320DM647, DM648 DSP manual DDR2 Memory Controller Signal Descriptions, Pin Description

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Mode Register Set MRS and Emrs Refresh ModeDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COL Activation Actv Ddrcs Ddrras Ddrcas Ddrwe Dcab Command Deactivation Dcab and Deac Read Command DDR2 Read Command Write WRT Command Memory Width and Byte AlignmentAddressable Memory Ranges Memory Width Maximum Addressable Bytes Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description DDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced Concept Command Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level Description Self-Refresh Mode Reset ConsiderationsReset Sources 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization 11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 Sdram Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Function Selection DDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration SDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description DDR2 Memory Controller Registers Offset Acronym Register Description Module ID and Revision Register Midr DDR2 Memory Controller Status Register DmcstatModule ID and Revision Register Midr Field Descriptions Bit Field Value Description Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Tsxnr Tsxrd Trtp Tcke Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl Rese Table A-1. Document Revision History Additions/Modifications/Deletions Products Applications DSPRfid