Activation Actv | Texas Instruments DM648 DSP, TMS320DM647 manual

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Peripheral Architecture

Figure 4. Refresh Command

REFR

DDR_CLK

DDR_CLK

DDR_CKE

DDR_CS

DDR_RAS

DDR_CAS

DDR_WE

DDR_A[13:0]

DDR_BA[2:0]

DDR_DQM[3:0]

2.4.3Activation (ACTV)

The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects the row. When the DDR2 memory controller issues an ACTV command, a delay of tRCD is incurred before a read or write command is issued. Figure 5 shows an example of an ACTV command. Reads or writes to the currently active row and bank of memory can achieve much higher throughput than reads or writes to random areas because every time a new row is accessed, the ACTV command must be issued and a delay of tRCD incurred.

Figure 5. ACTV Command

DDR_CLK

ACTV

DDR_CLK

DDR_CKE

DDR_CS

DDR_RAS

DDR_CAS

DDR_WE

DDR_A[13:0]

ROW

DDR_BA[2:0]

BANK

DDR_DQM[3:0]

SPRUEK5A –October 2007

DSP DDR2 Memory Controller

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Texas Instruments DM648 DSP, TMS320DM647 manual Activation Actv, Ddrcs Ddrras Ddrcas Ddrwe

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function COL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory Ranges Ibank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency Levels Self-Refresh Mode Reset ConsiderationsReset Sources 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 Configuration Edma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register Sdrfc SDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2 Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet Parameter Offset Acronym Register Description DDR2 Memory Controller Registers Bit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field Descriptions Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Tras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWR DDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt Tsxnr Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise Rese DDR2 Memory Controller Control Register Dmcctl Additions/Modifications/Deletions Table A-1. Document Revision History Products Applications DSPRfid