List of Tables | Texas Instruments DM648 DSP, TMS320DM647 manual

	List of Tables
1	DDR2 Memory Controller Signal Descriptions	12
2	DDR2 SDRAM Commands	13
3	Truth Table for DDR2 SDRAM Commands	13
4	Addressable Memory Ranges	18
5	Bank Configuration Register Fields for Address Mapping	19
6	DDR2 Memory Controller FIFO Description	22
7	Refresh Urgency Levels	25
8	Reset Sources	26
9	DDR2 SDRAM Mode Register Configuration	27
10	DDR2 SDRAM Extended Mode Register 1 Configuration	27
11	SDCFG Configuration	33
12	DDR2 Memory Refresh Specification	34
13	SDRFC Configuration	34
14	SDTIM1 Configuration	34
15	SDTIM2 Configuration	35
16	DMCCTL Configuration	35
17	DDR2 Memory Controller Registers	36
18	Module ID and Revision Register (MIDR) Field Descriptions	37
19	DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions	37
20	SDRAM Configuration Register (SDCFG) Field Descriptions	38
21	SDRAM Refresh Control Register (SDRFC) Field Descriptions	40
22	SDRAM Timing 1 Register (SDTIM1) Field Descriptions	41
23	SDRAM Timing 2 Register (SDTIM2) Field Descriptions	43
24	Burst Priority Register (BPRIO) Field Descriptions	44
25	DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions	45
A-1	Document Revision History	46

SPRUEK5A –October 2007

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Texas Instruments DM648 DSP, TMS320DM647 manual List of Tables

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal Descriptions Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Mode Register Set MRS and EmrsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COL Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width and Byte Alignment Write WRT CommandAddressable Memory Ranges Memory Width Maximum Addressable Bytes Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Sources Self-Refresh ModeReset Considerations DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization 11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Function Selection Sdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration Dmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description Offset Acronym Register Description DDR2 Memory Controller Registers DDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Bit Field Value Description Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Tsxnr Tsxrd Trtp Tcke Prioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions Rese DDR2 Memory Controller Control Register Dmcctl Additions/Modifications/Deletions Table A-1. Document Revision History Rfid Products ApplicationsDSP