Texas Instruments DM648 DSP, TMS320DM647 specs

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EDMA BUS

Peripheral Architecture

Figure 15. DDR2 Memory Controller FIFO Block Diagram

	Command FIFO	Command/Data	Command
	Command FIFO	Scheduler	to Memory
		Scheduler	to Memory
	Write FIFO
			Write Data
			to Memory
	Read FIFO
			Read Data
			from
			Memory
		Registers
	Command
	Data

2.7.1Command Ordering and Scheduling, Advanced Concept

The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data, address, and command buses while hiding the overhead of opening and closing DDR2 SDRAM rows. Command re-ordering takes place within the command FIFO.

The DDR2 memory controller examines all the commands stored in the command FIFO to schedule commands to the external memory. For each master, the DDR2 memory controller reorders the commands based on the following rules:

∙Selects the oldest command

∙A read command is advanced before an older write command if the read is to a different block address (2048 bytes) and the read priority is equal to or greater than the write priority.

Note: Most masters issue commands on a single priority level. Also, the EDMA transfer controller read and write ports are considered different masters, and thus, the above rule does not apply.

The second bullet above may be viewed as an exception to the first bullet. This means that for an individual master, all of its commands will complete from oldest to newest, with the exception that a read may be advanced ahead of an older, lower or equal priority write. Following this scheduling, each master may have one command ready for execution.

SPRUEK5A –October 2007

DSP DDR2 Memory Controller

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Texas Instruments DM648 DSP DDR2 Memory Controller Fifo Block Diagram, Command Ordering and Scheduling, Advanced Concept

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal Descriptions Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function COL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory Ranges Ibank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency Levels Reset Sources Self-Refresh ModeReset Considerations 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 Configuration Edma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register Sdrfc SDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2 Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet Parameter Offset Acronym Register Description DDR2 Memory Controller Registers Bit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field Descriptions Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Tras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWR DDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt Tsxnr Prioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions Rese DDR2 Memory Controller Control Register Dmcctl Additions/Modifications/Deletions Table A-1. Document Revision History Rfid Products ApplicationsDSP