SDTIM2 Configuration | Texas Instruments DM648 DSP, TMS320DM647

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Using the DDR2 Memory Controller

Table 15. SDTIM2 Configuration

	DDR2 SDRAM Data
Register Field	Sheet Parameter		Data Sheet	Formula (Register	Field
Name	Name	Description	Value	Field Must Be ≥)	Value
T_ODT	tAOND	tAOND specifies the ODT	2 (tCK cycles)	CAS latency - tAOND - 1	1
		turn-on delay
T_SXNR	tSXNR	Exit self refresh to a non-read	137.5 nS	(tSXNR × fDDR2_CLK) - 1	36
		command
T_SXRD	tSXRD	Exit self refresh to a read	200 (tCK cycles)	(tSXRD) - 1	199
		command
T_RTP	tRTP	Read to precharge command	7.5 nS	(tRTP × fDDR2_CLK) - 1	1
		delay
T_CKE	tCKE	CKE minimum pulse width	3 (tCK cycles)	(tCKE) - 1	2

3.2.4Configuring the DDR2 Memory Controller Control Register (DMCCTL)

The DDR2 memory controller control register (DMCCTL) contains a read latency (RL) field that helps the DDR2 memory controller determine when to sample read data. The RL field should be programmed to a value equal to CAS latency plus 1. For example, if a CAS latency of 4 is used, then RL should be programmed to 5.

Table 16. DMCCTL Configuration

		Register
Register Field Name	Description	Value
IFRESET	Programmed to be out of reset.	0
RL	Read latency is equal to CAS latency plus 1.	5

SPRUEK5A –October 2007	DSP DDR2 Memory Controller	35
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Texas Instruments DM648 DSP SDTIM2 Configuration, Dmcctl Configuration, DDR2 Sdram Data Register Field Sheet Parameter

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal Descriptions Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function COL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory Ranges Ibank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency Levels Reset Sources Self-Refresh ModeReset Considerations 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 Configuration Edma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register Sdrfc SDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2 Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet Parameter Offset Acronym Register Description DDR2 Memory Controller Registers Bit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field Descriptions Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Tras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWR DDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt Tsxnr Prioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions Rese DDR2 Memory Controller Control Register Dmcctl Additions/Modifications/Deletions Table A-1. Document Revision History Rfid Products ApplicationsDSP