Texas Instruments TMS320DM647, DM648 DSP manual

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DDR2 Memory Controller Registers

4.4SDRAM Refresh Control Register (SDRFC)

The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to:

∙Enter and Exit the self-refresh state.

∙Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands.

The SDRFC is shown in Figure 23 and described in Table 21.

			Figure 23. SDRAM Refresh Control Register (SDRFC)
31	30	29	16
SR	Rsvd		Reserved
R/W-	R/W-		R-0x0
0x0	0x0
15			0
			REFRESH_RATE
			R/W-0x753

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 21. SDRAM Refresh Control Register (SDRFC) Field Descriptions

Bit	Field	Value	Description
31	SR		Self-refresh bit. Writing a 1 to this bit will cause connected SDRAM devices to be place into Self
			Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state.
		0	Exit self-refresh mode.
		1	Enter self-refresh mode.
30	Reserved		Reserved. Writes to this register must keep this field at its default value.
29-16	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15-0	REFRESH_RATE		Refresh rate bits. The value in this field is used to define the rate at which connected SDRAM
			devices will be refreshed as follows: effect.

SDRAM refresh rate = DDR_CLK clock rate / REFRESH_RATE

Writing a value less than 0x0100 to this field will cause it to be loaded with 2 * T_RFC value from the SDRAM Timing 1 Register.

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DSP DDR2 Memory Controller

SPRUEK5A –October 2007

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Texas Instruments TMS320DM647, DM648 DSP manual Sdram Refresh Control Register Sdrfc

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Mode Register Set MRS and Emrs Refresh ModeDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COL Activation Actv Ddrcs Ddrras Ddrcas Ddrwe Dcab Command Deactivation Dcab and Deac Read Command DDR2 Read Command Write WRT Command Memory Width and Byte AlignmentAddressable Memory Ranges Memory Width Maximum Addressable Bytes Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description DDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced Concept Command Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level Description Reset Considerations Self-Refresh ModeReset Sources 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization 11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 Sdram Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Function Selection DDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration SDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description DDR2 Memory Controller Registers Offset Acronym Register Description Module ID and Revision Register Midr DDR2 Memory Controller Status Register DmcstatModule ID and Revision Register Midr Field Descriptions Bit Field Value Description Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Tsxnr Tsxrd Trtp Tcke Burst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl Rese Table A-1. Document Revision History Additions/Modifications/Deletions DSP Products ApplicationsRfid