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POST Code | Function | Phase | Component |
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0x09 | TCG log event failed | DXE | TCG |
0x09 | Setup event log failed | DXE | TCG |
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0x12 | TIS set active locality failed | DXE | TCG |
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0x12 | TIS relinquish active locality failed | DXE | TCG |
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0x12 | TIS wait command ready failed (prepare to send) | DXE | TCG |
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0x12 | TIS abort 'send’ command due to timeout | DXE | TCG |
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0x12 | TIS abort 'sendAndGo' command due to timeout | DXE | TCG |
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0x04 | TIS wait bit set failed before send last byte | DXE | TCG |
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0x12 | TIS abort command due to timeout before send last | DXE | TCG |
| byte |
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0x04 | TIS wait bit clear failed when sending last byte | DXE | TCG |
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0x22 | TCG Physical Presence execution | DXE | TCG |
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0xB1 | TCG DXE common pass through | DXE | TCG |
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0xE3 | First Legacy BIOS Task table for legacy reset | LBT | Core |
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0x20 | Verify that DRAM refresh is operating by polling the | LBT | Core |
| refresh bit in PORTB. |
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0xDA | Dummy PCIE Init entry, now handled by driver | LBT | Core |
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0x29 | PMM (POST Memory Manager) init | LBT | Core |
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0xE5 | WHEA init | LBT | Core |
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0x33 | PDM (Post Dispatcher Manager) init | LBT | Core |
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0x01 | IPMI init | LBT | Core |
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0xD8 | ASF Init | LBT | Core |
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0x09 | Set | LBT | Core |
| POST. If this bit is not cleared by |
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| postClearBootFlagJ (AEh), the TrustedCore on next |
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| boot determines that the current configuration |
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| caused POST to fail and uses default values for |
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| configuration. |
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0x2B | Enhanced CMOS init | LBT | Core |
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0xE0 | EFI Variable Init | LBT | Core |
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0xC1 | PEM (Post Error Manager) init | LBT | Core |
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0x3B | Debug Service Init (ROM Polit) | LBT | Core |
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0xDC | POST Update Error | LBT | Core |
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0x3A | Autosize external cache and program cache size for | LBT | Core |
| enabling later in POST. |
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0x0B | Enable CPU cache. Set bits in cmos related to | LBT | Core |
| cache. |
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0x0F | Enable the local bus IDE as primary or secondary | LBT | Core |
| depending on other drives detected. |
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0x10 | Initialize Power Management. | LBT | Core |
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0x14 | Verify that the 8742 keyboard controller is | LBT | Core |
| responding. Send a |
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| and wait for results. Also read the switch inputs from |
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| the 8742 and write the keyboard controller command |
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| byte. |
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Chapter 4 | 137 |