Post Codes
These tables describe the POST codes and descriptions during the POST.
Post Code Range
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SEC |
| 0x01 - 0x0F |
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PEI |
| 0x70 - 0x9F |
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DXE |
| 0x40 - 0x6F |
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BDS |
| 0x10 - 0x3F |
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SMM |
| 0xA0 - 0xBF |
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S3 |
| 0xC0 - 0xCF |
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ASL |
| 0x51 – 0x55 |
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| 0xE1 – 0xE4 |
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PostBDS |
| 0xF9 – 0xFE |
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Reserved |
| 0xD8 – 0xE0 |
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| 0xE5 – 0xE8 |
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SEC Phase POST Code Table |
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Functionality Name (Include\ |
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| Phase | Post |
| Description | |
PostCode.h) |
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SEC_SYSTEM_POWER_ON |
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| SEC | 1 | CPU power on and switch to | ||
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| Protected mode | |
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SEC_BEFORE_MICROCODE_PATCH |
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| SEC | 2 | Patching CPU microcode | ||
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SEC_AFTER_MICROCODE_PATCH |
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| SEC | 3 | Setup Cache as RAM | ||
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SEC_SETUP_CAR_OK |
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| SEC | 7 | Cache as RAM test | ||
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SEC_GO_TO_SECSTARTUP |
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| SEC | 9 | Setup BIOS ROM cache | ||
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SEC_GO_TO_PEICORE |
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| SEC | 0A | Enter Boot Firmware Volume | ||
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PEI Phase POST Code Table: |
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Functionality Name (Include\ |
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| Phase | Post |
| Description | |
PostCode.h) |
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PEI_SIO_INIT |
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| PEI | 70 | Super I/O Initialization | ||
PEI_CPU_REG_INIT |
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| PEI | 71 | CPU Early Initialization | ||
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PEI_CPU_AP_INIT |
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| PEI | 72 | |||
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PEI_CPU_HT_RESET |
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| PEI | 73 | HyperTransport Initialization | ||
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PEI_PCIE_MMIO_INIT |
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| PEI | 74 | PCIE MMIO BAR Initialization | ||
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PEI_NB_REG_INIT |
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| PEI | 75 | North Bridge Early Initialization | ||
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PEI_SB_REG_INIT |
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| PEI | 76 | South Bridge Early Initialization | ||
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PEI_PCIE_TRAINING |
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| PEI | 77 | PCIE Training | ||
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PEI_TPM_INIT |
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| PEI | 78 | TPM Initialization | ||
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PEI_SMBUS_INIT |
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| PEI | 79 | SMBUS Early Initialization | ||
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PEI_PROGRAM_CLOCK_GEN |
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| PEI | 7A | Clock Generator Initialization | ||
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PEI_MEMORY_INIT |
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| PEI | 7E | Memory Initial for Normal boot. | ||
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PEI_MEMORY_INIT_FOR_CRISIS |
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| PEI | 7F | Memory Initial for Crisis Recovery | ||
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PEI_MEMORY_INSTALL |
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| PEI | 80 | Simple Memory test | ||
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PEI_SWITCH_STACK |
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| PEI | 82 | Start to use Memory | ||
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Chapter 4 | 151 |
