Advantech IPPC-9150, IPPC-9120 user manual Sdram Data Integrity Mode

SDRAM Data Integrity Mode

When set as Non-ECC, supports standard 64-bit DIMM RAM modules. When set as ECC, supports standard 72-bit ECC RAM modules.

The options are: Non-ECC (Default), ECC.

System BIOS Cacheable

When enabled, allows the ROM area FOOOH-FFFFH to be cacheable when the cache controller is activated. The recommended setting is "Disabled", especially for high speed CPUs (200 MHz and above).

Video BIOS Cacheable

When enabled, allows the system to use the video BIOS codes from SRAMs, instead of the slower DRAMs or ROMs.

The options are: Enabled (Default), Disabled.

Video RAM Cacheable

Enables video RAM to be cacheable.

The options are: Disabled (Default), Enabled.

16 Bit I/O Recovery Time

Sets 16-bit I/O signal recovery time.

The options are: 1 (Default), 2, 3, 4, N/A.

Memory Hole at 15M-16M

When enabled, the memory hole at the 15 MB address will be relocated to the 15 ~ 16 MB address range of the ISA cycle when the processor accesses the 15 ~ 16 MB address area.

When disabled, the memory hole at the 15 MB address will be treated as a DRAM cycle when the processor accesses the 15 ~ 16 MB address.

The options are: Disabled (Default), Enabled.

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