Appendix D. Bit and Frame Error Rates The flow diagram below illustrates the decision processing performed by the
MT8850A/MT8852A in determining bit and frame error rates.
Start
Packet
Received
Decode Header
HEC Check NULL with
NAK
CRC
FER Count
CRC +1
LENGTH +1
FER Count
CRC +1
LENGTH FER Count
LENGTH +1
BER
Payload
END
FER Count
Lost +1
FER Count
LOST +1
Pass
Pass
Pass
Fail
Fail
Fail
NO
NO
Yes
Yes Sync found
END