Apollo 120 III, 150 III Sdram RAS Active Time, Sdram RAS Precharge Time, RAS to CAS Delay

User Manual version 2305

uADVANCED DRAM CONTROL 1 / 2 SETTINGS

The first chipset settings deal with CPU access to dynamic random access memory (DRAM). The default timings have been carefully chosen and should only be altered if data is being lost. Such a scenario might well occur if your system had mixed speed DRAM chips installed so that greater delays may be required to preserve the integrity of the data held in the slower memory chips.

uAUTO CONFIGURATION

This item will automatically configure the chipset timing. You may select 'manual' to set up following gray items by your specific need.

The choice: Manual, Auto, 100MHz or 133MHZ.

uSDRAM RAS ACTIVE TIME

This item defines SDRAM ACT to PRE command period. The Choice: 6T, 7T, 5T, 4T.

uSDRAM RAS Precharge Time

This item defines SDRAM PRE to ACT command period. The Choice: 3T, 2T, 4T, Reserved.

uRAS TO CAS DELAY

This item defines SDRAM ACT to Read/Write command period.

The choice: 3T, 2T, 4T, Reserved.

uDRAM BACKGROUND COMMAND

This item is lead-off time control for DRAM background command. When select 'Delay 1T', background commands are issued 1 clock behind memory address (MA) been issued. When select 'Normal', background command and MA are issued at the same time.

The choice: Delay 1T or Normal.

7-118 APOLLO 120/150 III