Connect Tech 
List of Tables | 
  | 
Table 1:   | 7  | 
Table 2: Slot Selection (RSW1)  | 8  | 
Table 3: FPGA Configuration Settings (J1)  | 8  | 
Table 4: JTAG Programming Header Pinout (P2)  | 9  | 
Table 5: SPI Flash Programming Header Pinout (P3)  | 9  | 
Table 6:   | 10  | 
Table 7:   | 10  | 
Table 8: External Power Connector Pinout (P8)  | 10  | 
Table 9: GPIO Header Pinout  | 11  | 
Table 10: Bar Local Address Space 0 (Bar 2)  | 24  | 
Table 11: Local Address Space 1 (Bar 3)  | 25  | 
List of Figures | 
  | 
Figure 1:  | 6  | 
Figure 2:  | 7  | 
Figure 3: External Power Connection | 10  | 
Revision 0.00 | 5  |