Cypress CY14B101K manual Min Max, Parameter Sram Write Cycle

CY14B101K

AC Switching Characteristics (continued)

Parameter		Description	25 ns		35 ns		45 ns		Unit
Cypress	Alt.		Min	Max	Min	Max	Min	Max
Parameter	Parameter
SRAM Write	Cycle
tWC	tAVAV	Write Cycle Time	25		35		45		ns
tPWE	tWLWH, tWLEH	Write Pulse Width	20		25		30		ns
tSCE	tELWH, tELEH	Chip Enable To End of Write	20		25		30		ns
tSD	tDVWH, tDVEH	Data Setup to End of Write	10		12		15		ns
tHD	tWHDX, tEHDX	Data Hold After End of Write	0		0		0		ns
tAW	tAVWH, tAVEH	Address Setup to End of Write	20		25		30		ns
tSA	tAVWL, tAVEL	Address Setup to Start of Write	0		0		0		ns
tHA	tWHAX, tEHAX	Address Hold After End of Write	0		0		0		ns
tHZWE [13, 16]	tWLQZ	Write Enable to Output Disable		10		13		15	ns
tLZWE [13]	tWHQX	Output Active After End of Write	3		3		3		ns

Figure 10. SRAM Write Cycle 1: WE Controlled [15, 17]

	tWC
ADDRESS
	tSCE
CE
	tAW
	tSA
WE	tPWE
	tSD
DATA IN	DATA VALID
	tHZWE
	HIGH IMPEDANCE

DATA OUT PREVIOUS DATA

tHA

tHD

tLZWE

Figure 11. SRAM Write Cycle 2: CE Controlled

ADDRESS

CE

WE

DATA IN

DATA OUT

tSA

tWC

tSCE tHA

tAW

tPWE

tSD tHD

DATA VALID

HIGH IMPEDANCE

Notes

16.If WE is Low when CE goes Low, the outputs remain in the High Impedance State.

17.CE or WE are greater than VIH during address transitions.

Document Number: 001-06401 Rev. *I Page 18 of 28

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