CY14B101K
Document Number: 001-06401 Rev. *I Page 17 of 28
AC Switching Characteristics
Parameter Description 25 ns 35 ns 45 ns Unit
Min Max Min Max Min Max
Cypress
Parameter Alt.
Parameter
SRAM Read Cycle
tACE tELQV Chip Enable Access Time 25 35 45 ns
tRC [11] tAVAV, tELEH Read Cycle Time 25 35 45 ns
tAA [12] tAVQV Address Access Time 25 35 45 ns
tDOE tGLQV Output Enable to Data Valid 12 15 20 ns
tOHA [12] tAXQX Output Hold After Address Change 3 3 3 ns
tLZCE [13] tELQX Chip Enable to Output Active 3 3 3 ns
tHZCE [13] tEHQZ Chip Disable to Output Inactive 10 13 15 ns
tLZOE [13] tGLQX Output Enable to Output Active 0 0 0 ns
tHZOE [13] tGHQZ Output Disable to Output Inactive 10 13 15 ns
tPU [14] tELICCH Chip Enable to Power Active 0 0 0 ns
tPD [14] tEHICCL Chip Disable to Power Standby 25 35 45 ns
Figure 8. SRAM Read Cycle 1: Address Controlled [11, 12, 15]
Figure 9. SRAM Read Cycle 2: CE and OE Controlled [11, 15]
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Notes
11. WE is HIGH during SRAM Read Cycles.
12.Device is continuously selected with CE and OE both Low.
13.Measured ±200 mV from steady state output voltage.
14.These parameters are guaranteed by design and are not tested.
15.HSB must remain HIGH during READ and WRITE cycles.
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