Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY14B104L Package Diagrams continued, 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm, + Feedback

Models: CY14B104L CY14B104N

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CY14B104L, CY14B104N

Package Diagrams (continued)

Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)

TOP VIEW

A1 CORNER

1 2 3 4 5 6

BOTTOM VIEW

A1 CORNER

Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
6	5	4	3	2	1

			A
			B
			B
	10.00±0.10		C
	10.00±0.10		D
			D
			E
			F
			G
			H


	A

		B
	0.53±0.05

0.25 C

0.36

6.00±0.10

0.21±0.05
0.21±0.05						0.15 C

SEATING PLANE

1.20 MAX

10.00±0.10

		A
		B
	0.75	C
5.25		D
5.25		E
		E
	2.625	F
	2.625	G
		G
		H
		1.875
		0.75
		3.75
	B	6.00±0.10
	0.15(4X)
		51-85128-*D

Document #: 001-07102 Rev. *L

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Cypress manual Package Diagrams continued, 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm, CY14B104L, CY14B104N, + Feedback

Contents

Features Logic Block Diagram1, 2CY14B104L, CY14B104N Functional DescriptionFigure 1. Pin Diagram - 48 FBGA Figure 2. Pin Diagram - 44 Pin TSOPPinouts 44 - TSOPFigure 3. Pin Diagram - 54 Pin TSOP II Output Enable, Active LOW. The active LOWByte High Enable, Active LOW. Controls DQ15 - DQ8 Byte Low Enable, Active LOW. Controls DQ7 - DQ0Figure 4. AutoStore Mode Device OperationSRAM Read SRAM WriteHardware RECALL Power Up Table 1. Mode SelectionPower Software STORETable 1. Mode Selection continued Preventing AutoStoreData Protection Noise ConsiderationsDC Electrical Characteristics Maximum RatingsOperating Range RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsParameters 20 nsCY14B104L, CY14B104N Figure 7. SRAM Read Cycle #2 CE and OE Controlled 3, 14Figure 8. SRAM Write Cycle #1 WE Controlled3, 17, 18 + FeedbackFigure 9. SRAM Write Cycle #2 CE Controlled 3, 17, 18 Figure 10. SRAM Write Cycle #3 BHE and BLE Controlled3, 17, 18CY14B104L, CY14B104N + FeedbackAutoStore/Power Up RECALL Figure 11. AutoStore or Power Up RECALL23CY14B104L/CY14B104N Switching WaveformsFigure 13. Autostore Enable / Disable Cycle Software Controlled STORE/RECALL CycleFigure 12. CE and OE Controlled Software STORE/RECALL Cycle26 Switching WaveformsHardware STORE Cycle Hardware STORE Pulse WidthHardware STORE LOW to STORE Busy Figure 14. Hardware STORE Cycle21For x8 Configuration For x16 ConfigurationTruth Table For SRAM Operations Inputs/Outputs2Diagram Ordering InformationSpeed Ordering CodeOrdering Information continued DiagramCY14B104L, CY14B104N SpeedCY14B104L, CY14B104N Part Numbering NomenclatureCY 14 B 104 L - ZS P 20 X C T Package Diagrams Figure 16. 44-Pin TSOP IICY14B104L, CY14B104N + FeedbackPackage Diagrams continued Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mmCY14B104L, CY14B104N + FeedbackFigure 18. 54-Pin TSOP II Package Diagrams continuedCY14B104L, CY14B104N Page 21 ofDocument History Page Document Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAMDocument Number ECN NoCY14B104L, CY14B104N Document Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAMDocument Number ECN NoCY14B104L, CY14B104N Document Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAMDocument Number ECN NoSales, Solutions, and Legal Information PSoC SolutionsWorldwide Sales and Design Support Products