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Cypress Hardware STORE Pulse Width, Hardware STORE Cycle21, CY14B104L, CY14B104N, Unit

Models: CY14B104L CY14B104N

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CY14B104L, CY14B104N

Hardware STORE Cycle

Parameters	Description	CY14B104L/CY14B104N		Unit
Parameters	Description	Min	Max	Unit
		Min	Max
tPHSB	Hardware STORE Pulse Width	15		ns
tHLBL	Hardware STORE LOW to STORE Busy		500	ns

Switching Waveforms

Figure 14. Hardware STORE Cycle[21]

:ULWHODWFKVHW

+6%,1

+6%287

W3+6%

W6725(

W+/%/

W'(/$<

W+++'

W/=+6%

'4'DWD2XW

:ULWHODWFKQRWVHW

+6%,1

+6%287

W3+6%

W+/%/

W'(/$<

W+++'

'4'DWD2XW

Figure 15. Soft Sequence Processing[27, 28]

	6RIW6HTXHQFH		W66	6RIW6HTXHQFH		W66
	&RPPDQG			&RPPDQG
$GGUHVV	$GGUHVV	$GGUHVV		$GGUHVV	$GGUHVV
	W6$		W&:		W&:
&(
9&&

Notes

27.This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command.

28.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-07102 Rev. *L

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Cypress Hardware STORE Cycle, Hardware STORE Pulse Width, Hardware STORE LOW to STORE Busy, CY14B104L, CY14B104N, Unit

Contents

CY14B104L, CY14B104N FeaturesLogic Block Diagram1, 2 Functional DescriptionPinouts Figure 1. Pin Diagram - 48 FBGAFigure 2. Pin Diagram - 44 Pin TSOP 44 - TSOPByte High Enable, Active LOW. Controls DQ15 - DQ8 Figure 3. Pin Diagram - 54 Pin TSOP IIOutput Enable, Active LOW. The active LOW Byte Low Enable, Active LOW. Controls DQ7 - DQ0SRAM Read Figure 4. AutoStore ModeDevice Operation SRAM WritePower Hardware RECALL Power UpTable 1. Mode Selection Software STOREData Protection Table 1. Mode Selection continuedPreventing AutoStore Noise ConsiderationsOperating Range DC Electrical CharacteristicsMaximum Ratings RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsParameters AC Switching CharacteristicsSwitching Waveforms 20 nsFigure 8. SRAM Write Cycle #1 WE Controlled3, 17, 18 CY14B104L, CY14B104NFigure 7. SRAM Read Cycle #2 CE and OE Controlled 3, 14 + FeedbackCY14B104L, CY14B104N Figure 9. SRAM Write Cycle #2 CE Controlled 3, 17, 18Figure 10. SRAM Write Cycle #3 BHE and BLE Controlled3, 17, 18 + FeedbackCY14B104L/CY14B104N AutoStore/Power Up RECALLFigure 11. AutoStore or Power Up RECALL23 Switching WaveformsFigure 12. CE and OE Controlled Software STORE/RECALL Cycle26 Figure 13. Autostore Enable / Disable CycleSoftware Controlled STORE/RECALL Cycle Switching WaveformsHardware STORE LOW to STORE Busy Hardware STORE CycleHardware STORE Pulse Width Figure 14. Hardware STORE Cycle21Truth Table For SRAM Operations For x8 ConfigurationFor x16 Configuration Inputs/Outputs2Speed DiagramOrdering Information Ordering CodeCY14B104L, CY14B104N Ordering Information continuedDiagram SpeedCY14B104L, CY14B104N Part Numbering NomenclatureCY 14 B 104 L - ZS P 20 X C T CY14B104L, CY14B104N Package DiagramsFigure 16. 44-Pin TSOP II + FeedbackCY14B104L, CY14B104N Package Diagrams continuedFigure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm + FeedbackCY14B104L, CY14B104N Figure 18. 54-Pin TSOP IIPackage Diagrams continued Page 21 ofDocument Number Document History PageDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM ECN NoDocument Number CY14B104L, CY14B104NDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM ECN NoDocument Number CY14B104L, CY14B104NDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM ECN NoWorldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Products