51-85160 | Cypress CY14B104N, CY14B104L instruction

CY14B104L, CY14B104N

Figure 18. 54-Pin TSOP II (51-85160)

Document #: 001-07102 Rev. *L

Page 21 of 25

[+] Feedback

Image 21

Contents

Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor Corporation Top View PinoutsNot to scale Tsop Pin Definitions Sram Read Device OperationSram Write AutoStore Operation Mode Selection Hardware Recall Power UpA15 A07 Mode Power Software Store Preventing AutoStore Mode Selection A15 A07 PowerData Protection Noise Considerations Maximum Ratings DC Electrical CharacteristicsOperating Range Range Capacitance Data Retention and EnduranceThermal Resistance AC Test Conditions Switching Waveforms AC Switching CharacteristicsMin Max Sram Read Cycle CY14B104L, CY14B104N Sram Write Cycle #2 CE Controlled 3, 17, 18 AutoStore/Power Up Recall Parameters Description CY14B104L/CY14B104N Unit Min MaxHSB Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle Hardware Store Cycle Hardware Store Pulse WidthHardware Store LOW to Store Busy 500 Inputs/Outputs2 Mode Power Truth Table For Sram OperationsHigh Z Ordering Information CY14B104L-ZS45XIT CY14B104L-ZS45XCTCY14B104L-BA45XCT CY14B104L-BA45XIT CY 14 B 104 L ZS P 20 X C T Part Numbering NomenclatureZS Tsop Nvsram Pin Tsop II Package Diagrams Ball Fbga 6 mm x 10 mm x 1.2 mm 51-85160 TUP Document HistoryPCI UHA GVCH/PYRS GVCH/DSG Aesa USB Sales, Solutions, and Legal Information