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Cypress manual 54-Pin TSOP II, CY14B104L, CY14B104N, Package Diagrams continued, Page 21 of

Models: CY14B104L CY14B104N

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CY14B104L, CY14B104N

Package Diagrams (continued)

Figure 18. 54-Pin TSOP II (51-85160)

51-85160-**

Document #: 001-07102 Rev. *L

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Contents

Logic Block Diagram1, 2 FeaturesCY14B104L, CY14B104N Functional DescriptionFigure 2. Pin Diagram - 44 Pin TSOP Figure 1. Pin Diagram - 48 FBGAPinouts 44 - TSOPOutput Enable, Active LOW. The active LOW Figure 3. Pin Diagram - 54 Pin TSOP IIByte High Enable, Active LOW. Controls DQ15 - DQ8 Byte Low Enable, Active LOW. Controls DQ7 - DQ0Device Operation Figure 4. AutoStore ModeSRAM Read SRAM WriteTable 1. Mode Selection Hardware RECALL Power UpPower Software STOREPreventing AutoStore Table 1. Mode Selection continuedData Protection Noise ConsiderationsMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsParameters 20 nsFigure 7. SRAM Read Cycle #2 CE and OE Controlled 3, 14 CY14B104L, CY14B104NFigure 8. SRAM Write Cycle #1 WE Controlled3, 17, 18 + FeedbackFigure 10. SRAM Write Cycle #3 BHE and BLE Controlled3, 17, 18 Figure 9. SRAM Write Cycle #2 CE Controlled 3, 17, 18CY14B104L, CY14B104N + FeedbackFigure 11. AutoStore or Power Up RECALL23 AutoStore/Power Up RECALLCY14B104L/CY14B104N Switching WaveformsSoftware Controlled STORE/RECALL Cycle Figure 13. Autostore Enable / Disable CycleFigure 12. CE and OE Controlled Software STORE/RECALL Cycle26 Switching WaveformsHardware STORE Pulse Width Hardware STORE CycleHardware STORE LOW to STORE Busy Figure 14. Hardware STORE Cycle21For x16 Configuration For x8 ConfigurationTruth Table For SRAM Operations Inputs/Outputs2Ordering Information DiagramSpeed Ordering CodeDiagram Ordering Information continuedCY14B104L, CY14B104N SpeedPart Numbering Nomenclature CY 14 B 104 L - ZS P 20 X C TCY14B104L, CY14B104N Figure 16. 44-Pin TSOP II Package DiagramsCY14B104L, CY14B104N + FeedbackFigure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm Package Diagrams continuedCY14B104L, CY14B104N + FeedbackPackage Diagrams continued Figure 18. 54-Pin TSOP IICY14B104L, CY14B104N Page 21 ofDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Document History PageDocument Number ECN NoDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM CY14B104L, CY14B104NDocument Number ECN NoDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM CY14B104L, CY14B104NDocument Number ECN NoPSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products