CY14B104L, CY14B104N
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven LOW by the HSB driver.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B104L/CY14B104N software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence. Further, no read or write operations must be done after the sixth address read for a duration of
To initiate the software STORE cycle, the following addresses and read sequence must be performed.
1.Read Address 0x4E38 Valid READ
2.Read Address 0xB1C7 Valid READ
3.Read Address 0x83E0 Valid READ
4.Read Address 0x7C1F Valid READ
5.Read Address 0x703F Valid READ
6.Read Address 0x8FC0 Initiate STORE Cycle
Table 1. Mode Selection
The software sequence may be clocked with CE controlled reads or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB will be driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed.
1.Read Address 0x4E38 Valid READ
2.Read Address 0xB1C7 Valid READ
3.Read Address 0x83E0 Valid READ
4.Read Address 0x7C1F Valid READ
5.Read Address 0x703F Valid READ
6.Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
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| [3] | A15 - A0[7] | Mode | IO | Power |
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| WE | OE, | BHE, | BLE | |||||||||
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| X | X | Not Selected | Output High Z | Standby | |||
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| L | X | Read SRAM | Output Data | Active | |||
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| X | X | Write SRAM | Input Data | Active | |||
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| L | 0x4E38 | Read SRAM | Output Data | Active[8, 9] | |||
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| 0xB1C7 | Read SRAM | Output Data |
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| 0x83E0 | Read SRAM | Output Data |
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| 0x7C1F | Read SRAM | Output Data |
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| 0x703F | Read SRAM | Output Data |
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| 0x8B45 | AutoStore | Output Data |
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| Disable |
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Notes
7.While there are 19 address lines on the CY14B104L (18 address lines on the CY14B104N), only the 13 address lines (A14 - A2) are used to control software modes. The rest of the address lines are don’t care.
8.The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
9.IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
Document #: | Page 5 of 25 |
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