Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress SRAM Write Cycle #2 CE Controlled 3, 17, 18, CY14B104L, CY14B104N, + Feedback, Address

Models: CY14B104L CY14B104N

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Figure 9. SRAM Write Cycle #2: CE Controlled[3, 17, 18, 19]

		CY14B104L, CY14B104N
Figure 9. SRAM Write Cycle #2: CE Controlled[3, 17, 18, 19]
	tWC
Address	Address Valid
tSA	tSCE	tHA
CE
BHE, BLE	tBW
BHE, BLE
	tPWE
WE
	tSD	tHD

Data Input			Input Data Valid

High Impedance

Data Output

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 17, 18, 19]

	W:&
$GGUHVV	$GGUHVV9DOLG
	W6&(
&(
W6$	W%:	W+$
%+(%/(
	W$:
	W3:(
:(
	W6'	W+'
'DWD,QSXW	,QSXW'DWD9DOLG
	+LJK,PSHGDQFH
'DWD2XWSXW

Document #: 001-07102 Rev. *L

Page 11 of 25

[+] Feedback

Page 11

Image 11

Cypress CY14B104N manual SRAM Write Cycle #2 CE Controlled 3, 17, 18, SRAM Write Cycle #3 BHE and BLE Controlled3, 17, 18

Contents

Functional Description FeaturesLogic Block Diagram1, 2 CY14B104L, CY14B104N44 - TSOP Figure 1. Pin Diagram - 48 FBGAFigure 2. Pin Diagram - 44 Pin TSOP PinoutsByte Low Enable, Active LOW. Controls DQ7 - DQ0 Figure 3. Pin Diagram - 54 Pin TSOP IIOutput Enable, Active LOW. The active LOW Byte High Enable, Active LOW. Controls DQ15 - DQ8SRAM Write Figure 4. AutoStore ModeDevice Operation SRAM ReadSoftware STORE Hardware RECALL Power UpTable 1. Mode Selection PowerNoise Considerations Table 1. Mode Selection continuedPreventing AutoStore Data ProtectionRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal Resistance20 ns AC Switching CharacteristicsSwitching Waveforms Parameters+ Feedback CY14B104L, CY14B104NFigure 7. SRAM Read Cycle #2 CE and OE Controlled 3, 14 Figure 8. SRAM Write Cycle #1 WE Controlled3, 17, 18+ Feedback Figure 9. SRAM Write Cycle #2 CE Controlled 3, 17, 18Figure 10. SRAM Write Cycle #3 BHE and BLE Controlled3, 17, 18 CY14B104L, CY14B104NSwitching Waveforms AutoStore/Power Up RECALLFigure 11. AutoStore or Power Up RECALL23 CY14B104L/CY14B104NSwitching Waveforms Figure 13. Autostore Enable / Disable CycleSoftware Controlled STORE/RECALL Cycle Figure 12. CE and OE Controlled Software STORE/RECALL Cycle26Figure 14. Hardware STORE Cycle21 Hardware STORE CycleHardware STORE Pulse Width Hardware STORE LOW to STORE BusyInputs/Outputs2 For x8 ConfigurationFor x16 Configuration Truth Table For SRAM OperationsOrdering Code DiagramOrdering Information SpeedSpeed Ordering Information continuedDiagram CY14B104L, CY14B104NCY14B104L, CY14B104N Part Numbering NomenclatureCY 14 B 104 L - ZS P 20 X C T + Feedback Package DiagramsFigure 16. 44-Pin TSOP II CY14B104L, CY14B104N+ Feedback Package Diagrams continuedFigure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm CY14B104L, CY14B104NPage 21 of Figure 18. 54-Pin TSOP IIPackage Diagrams continued CY14B104L, CY14B104NECN No Document History PageDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Document NumberECN No CY14B104L, CY14B104NDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Document NumberECN No CY14B104L, CY14B104NDocument Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Document NumberProducts Sales, Solutions, and Legal InformationPSoC Solutions Worldwide Sales and Design Support

Figure 9. SRAM Write Cycle #2: CE Controlled[3, 17, 18, 19]

Address

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 17, 18, 19]