Cypress CY7C1163V18, CY7C1165V18 Application Example, Truth Table, Operation, Write Cycle Load

CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Application Example

Figure 1 shows four QDR-II+ used in an application.

Figure 1. Application Example

			SRAM #1		ZQ	RQ = 250ohms			ZQ	RQ = 250ohms
	Vt			CQ/CQ				SRAM #4	CQ/CQ
		D	RPS WPS BWS		Q		D		Q
	R	A		K	K		A	RPS WPS BWS	K K
DATA IN								R
DATA OUT
								Vt
Address								Vt
BUS MASTER	RPS							R
(CPU or ASIC)	WPS
	BWS
CLKIN/CLKIN
Source K
Source K								R = 50ohms, Vt = VDDQ/2

Truth Table

The truth table for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.[3, 4, 5, 6, 7, 8]

Operation	K	RPS	WPS	DQ		DQ		DQ	DQ
Write Cycle: Load	L-H	H[9]	L[10]	D(A) at K(t + 1) ↑		D(A + 1) at		D(A + 2) at K(t + 2) ↑
							K(t + 1) ↑		D(A + 3) at K(t + 2) ↑
address on rising edge of
K; input write data on two
consecutive K and K rising
edges.
Read Cycle (2.5 Cycle	L-H	L[10]	X	Q(A) at		Q(A + 1) at K(t + 3) ↑			Q(A + 3) at K(t + 4) ↑
					K(t + 2) ↑			Q(A + 2) at K(t + 3)↑
Latency): Load address on
rising edge of K; wait one
and a half cycle; read data
on two consecutive K and
K rising edges.
NOP: No operation.	L-H	H	H	D = X		D = X		D = X	D = X
				Q = High Z		Q = High Z		Q = High Z	Q = High Z
Standby: Clock stopped.	Stopped	X	X	Previous State		Previous State		Previous State	Previous State

Notes

2.The above application shows four QDR-II+ being used.

3.X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.

4.Device powers up deselected and the outputs in a tri-state condition.

5.“A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.

6.“t” represents the cycle at which a read or write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, respectively succeeding the “t” clock cycle.

7.Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.

8.It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

9.If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

10.This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request.

Document Number: 001-06582 Rev. *D Page 10 of 29

[+] Feedback