Cypress CY7C1176V18, CY7C1165V18, CY7C1163V18 Depth Expansion, Programmable Impedance, Echo Clocks

CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18

Depth Expansion

The CY7C1163V18 has a port select input for each port. This enables easy depth expansion. Both port selects are only sampled on the rising edge of the positive input clock (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II+ to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II+. CQ is referenced with respect to K and CQ is refer- enced with respect to K. These are free running clocks and are synchronized to the input clock of the QDR-II+. The timings for the echo clocks are shown in the AC timing table.

Valid Data Indicator (QVLD)

QVLD is provided on the QDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR-II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, “DLL Consid- erations in QDRII/DDRII/QDRII+/DDRII+.” The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be reset in order to lock to the desired frequency. During power up when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock.

Document Number: 001-06582 Rev. *D Page 9 of 29

[+] Feedback