Read Write NOP | Cypress CY7C1176V18, CY7C1165V18, CY7C1163V18

CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Switching Waveforms

Read/Write/Deselect Sequence

Figure 6. Waveform for 2.5 Cycle Read Latency[31, 32, 33]

NOP 1

tKH

	READ	WRITE	READ	WRITE	NOP
	2	3	4	5	6	7	8
tKL	tCYC	tKHKH

RPS
tSC tHC	t SC tHC

WPS

D QVLD

A0	A1	A2		A3
tSA tHA		tHD		tSD		tHD
		t SD		tSD
		D10	D11	D12	D13	D30	D31	D32	D33
									tQVLD
				tCO		tDOH			tCQDOH	tCHZ
		tCLZ		tCO		tCQD			tCQDOH
		tCLZ				tCQD

		Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23
(Read Latency = 2.5 Cycles)			t

		tCQOH	CCQO

tCQH tCQHCQH	tCQOH	t	CCQO

DON’T CARE

UNDEFINED

Notes

31.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

32.Outputs are disabled (High Z) one clock cycle after a NOP.

33.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-06582 Rev. *D

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Cypress CY7C1176V18, CY7C1165V18, CY7C1163V18, CY7C1161V18 manual Read Write NOP

Contents

Configurations FeaturesFunctional Description Selection Guide Logic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1161V18Doff Logic Block Diagram CY7C1165V18 Logic Block Diagram CY7C1163V18 CY7C1161V18 2M x Pin ConfigurationsCY7C1176V18 2M x NC/144M CY7C1165V18 512K x CY7C1163V18 1M xWPS BWS RPS Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for Jtag Read Operations Functional OverviewWrite Operations Byte Write Operations Depth Expansion Valid Data Indicator QvldProgrammable Impedance Echo Clocks Truth Table Application ExampleOperation Write Cycle Load Comments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequence Device Write cycle descriptions of CY7C1165V18 follows.3Into the device. D359 remains unaltered Device. D80 and D3518 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram12 TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max Unit TAP Timing and Test Conditions TAP AC Switching Characteristics Scan Register Sizes Identification Register DefinitionsInstruction Codes Bit # Bump ID Boundary Scan Order Power Up Sequence Power Up Sequence in QDR-II+ SRAPower Up Waveforms DLL Constraints AC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating Range Thermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max Unit Parameter Min Max Switching CharacteristicsHigh LOW Static to DLL Reset Clock Phase JitterParameter Min Max DLL Timing DLL Lock Time K Read Write NOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package Diagram Document History ECN No Issue Date Orig. Description of ChangeNXR VKN/KKVTMP

Figure 6. Waveform for 2.5 Cycle Read Latency[31, 32, 33]

READ

WRITE

NOP

WPS

DON’T CARE

UNDEFINED