Cypress CY7C1161V18, CY7C1163V18, CY7C1165V18, CY7C1176V18 CY7C1161V18, CY7C1176V18

CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D Page 17 of 29
TAP AC Switching Characteristics
The Tap AC Switching Characteristics over the operating range follows.[16, 17]
Parameter Description Min Max Unit
tTCYC TCK Clock Cycle Time 50 ns
tTF TCK Clock Frequency 20 MHz
tTH TCK Clock HIGH 20 ns
tTL TCK Clock LOW 20 ns
Setup Times
tTMSS TMS Setup to TCK Clock Rise 5 ns
tTDIS TDI Setup to TCK Clock Rise 5 ns
tCS Capture Setup to TCK Rise 5 ns
Hold Times
tTMSH TMS Hold after TCK Clock Rise 5 ns
tTDIH TDI Hold after Clock Rise 5 ns
tCH Capture Hold after Clock Rise 5 ns
Output Times
tTDOV TCK Clock LOW to TDO Valid 10 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
TAP Timing and Test Conditions
The Tap Timing and Test Conditions for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.[17]
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50 Ω
GND
0.9V
50 Ω
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Notes
16.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
17.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
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