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Cypress CY7C1161V18, CY7C1165V18 TAP Controller State Diagram, Tap Controller State Diagram12

Models: CY7C1161V18 CY7C1165V18 CY7C1176V18 CY7C1163V18

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CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

TAP Controller State Diagram

Figure 2. Tap Controller State Diagram[12]

TEST-LOGIC RESET

TEST-LOGIC/ IDLE

1	SELECT		1	SELECT		1
1	SELECT		1	SELECT
	DR-SCAN			IR-SCAN
	0			0
	1			1
	CAPTURE-DR			CAPTURE-IR
	0			0
	SHIFT-DR		0	SHIFT-IR		0
	1			1
	EXIT1-DR		1	EXIT1-IR		1
	EXIT1-DR			EXIT1-IR
	0			0
	PAUSE-DR		0	PAUSE-IR		0
	1			1
	0			0
	EXIT2-DR			EXIT2-IR
	1			1
	UPDATE-DR			UPDATE-IR
	1	0		1	0
		0			0

Note

12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document Number: 001-06582 Rev. *D

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Cypress CY7C1161V18, CY7C1165V18, CY7C1176V18, CY7C1163V18 manual TAP Controller State Diagram, Tap Controller State Diagram12

Contents

Selection Guide FeaturesConfigurations Functional Description Logic Block Diagram CY7C1161V18 Logic Block Diagram CY7C1176V18Doff Logic Block Diagram CY7C1165V18 Logic Block Diagram CY7C1163V18 NC/144M Pin ConfigurationsCY7C1161V18 2M x CY7C1176V18 2M x CY7C1163V18 1M x CY7C1165V18 512K xWPS BWS RPS Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for Jtag Byte Write Operations Functional OverviewRead Operations Write Operations Echo Clocks Valid Data Indicator QvldDepth Expansion Programmable Impedance Write Cycle Load Application ExampleTruth Table Operation During the data portion of a write sequence Write Cycle DescriptionsComments Remains unaltered Device. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1165V18 follows.3Device Into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram12 TAP Controller State Diagram Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP Controller TAP Timing and Test Conditions TAP AC Switching Characteristics Identification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan Order DLL Constraints Power Up Sequence in QDR-II+ SRAPower Up Sequence Power Up Waveforms Operating Range Electrical CharacteristicsAC Electrical Characteristics Maximum Ratings Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and Waveforms LOW Switching CharacteristicsParameter Min Max High DLL Lock Time K Clock Phase JitterStatic to DLL Reset Parameter Min Max DLL Timing Read Write NOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package Diagram VKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR