CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18
Functional Overview
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 are synchronous pipelined burst SRAMs equipped with both a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate read and write ports, the
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timings are referenced to the rising edge of the Input clocks (K/K).
All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the Input clocks (K and K) also.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K).
CY7C1163V18 is described in the following sections. The same basic descriptions apply to CY7C1161V18, CY7C1176V18, and CY7C1165V18.
Read Operations
The CY7C1163V18 is organized internally as four arrays of 256K x 18. Accesses are completed in a burst of four sequential
When the read port is deselected, the CY7C1163V18 first completes the pending read transactions. Synchronous internal circuitry automatically
Write Operations
Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise, the data presented to D[17:0] is latched and stored into the lower
When deselected, the write port ignores all inputs after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1163V18. A write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of
Concurrent Transactions
The read and write ports on the CY7C1163V18 operate completely independent of one another. Because each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle initiated on the previous K clock rise.
Read accesses and write access are scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the read port takes priority. If a read is initiated on the previous cycle, the write port assumes priority (because read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port assumes priority (because write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read or write operations initiated, with the first access being a read.
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