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Cypress CY7C1165V18, CY7C1176V18, CY7C1163V18 manual Package Diagram, Ball Fbga 13 x 15 x 1.4 mm

Models: CY7C1161V18 CY7C1165V18 CY7C1176V18 CY7C1163V18

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CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Package Diagram

Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

15.00±0.10

TOP VIEW

PIN 1 CORNER

15.00±0.10

BOTTOM VIEW

							PIN 1 CORNER
					Ø0.05 M C
						Ø0.25 M C A B
					Ø0.50		-0.06	(165X)
							+0.14
11	10	9	8	7	6	5	4	3	2	1
										A
										B
1.00										C
1.00										D
										D
										E
										F
14.00										G
14.00										H
										J
										K
7.00										L
7.00										M
										M

1.00

5.00

10.00

0.25 C

	B
0.53±0.05
0.36	C
0.36

13.00±0.10

		1.40MAX.
		1.40MAX.		0.15C

SEATING PLANE

0.35±0.06

B 13.00±0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC

51-85180-*A

Document Number: 001-06582 Rev. *D

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Cypress CY7C1165V18, CY7C1176V18, CY7C1163V18, CY7C1161V18 manual Package Diagram, Ball Fbga 13 x 15 x 1.4 mm

Contents

Features ConfigurationsFunctional Description Selection Guide Logic Block Diagram CY7C1176V18 Logic Block Diagram CY7C1161V18Doff Logic Block Diagram CY7C1163V18 Logic Block Diagram CY7C1165V18 Pin Configurations CY7C1161V18 2M xCY7C1176V18 2M x NC/144M CY7C1165V18 512K x CY7C1163V18 1M xWPS BWS RPS Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for Jtag Functional Overview Read OperationsWrite Operations Byte Write Operations Valid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo Clocks Application Example Truth TableOperation Write Cycle Load Write Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequence Write cycle descriptions of CY7C1165V18 follows.3 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram12 TAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max Unit TAP AC Switching Characteristics TAP Timing and Test Conditions Scan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump ID Power Up Sequence in QDR-II+ SRA Power Up SequencePower Up Waveforms DLL Constraints Electrical Characteristics AC Electrical CharacteristicsMaximum Ratings Operating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max Unit Switching Characteristics Parameter Min MaxHigh LOW Clock Phase Jitter Static to DLL ResetParameter Min Max DLL Timing DLL Lock Time K Read Write NOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document HistoryNXR VKN/KKVTMP