Cypress CY7C1161V18, CY7C1165V18 manual Switching Characteristics, Parameter Min Max, High, Low

CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

Switching Characteristics

Over the operating range[23, 24]

Cypress

Consortium

Description

400 MHz

375 MHz

333 MHz

300 MHz

Unit

Parameter

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

tPOWER

VDD(Typical) to the First Access[25]

1

–

1

–

1

–

1

–

ms

tCYC

tKHKH

K Clock Cycle Time

2.50

8.40

2.66

8.40

3.0

8.40

3.3

8.40

ns

tKH

tKHKL

tCYC

Input Clock (K/K)

HIGH

0.4

–

0.4

–

0.4

–

0.4

–

tKL

tKLKH

tCYC

Input Clock (K/K)

LOW

0.4

–

0.4

–

0.4

–

0.4

–

tKHKH

tKHKH

K Clock Rise to

Clock Rise

1.06

–

1.13

–

1.28

–

1.40

–

ns

K

(rising edge to rising edge)

Setup Times

tSA

tAVKH

Address Setup to K Clock Rise

0.4

–

0.4

–

0.4

–

0.4

–

ns

tSC

tIVKH

Control Setup to K Clock Rise

0.4

–

0.4

–

0.4

–

0.4

–

ns

(RPS,

WPS)

tSCDDR

tIVKH

Double Data Rate Control Setup to Clock (K,

0.28

–

0.28

–

0.28

–

0.28

–

ns

K)

Rise (BWS0, BWS1, BWS2, BWS3)

tSD

tDVKH

D[X:0] Setup to Clock (K/K)

Rise

0.28

–

0.28

–

0.28

–

0.28

–

ns

Hold Times

tHA

tKHAX

Address Hold after K Clock Rise

0.4

–

0.4

–

0.4

–

0.4

–

ns

tHC

tKHIX

Control Hold after K Clock Rise

0.4

–

0.4

–

0.4

–

0.4

–

ns

(RPS,

WPS)

tHCDDR

tKHIX

0.28

–

0.28

–

0.28

–

0.28

–

ns

Double Data Rate Control Hold after Clock (K/K)

Rise (BWS0, BWS1, BWS2, BWS3)

tHD

tKHDX

Rise

0.28

–

0.28

–

0.28

–

0.28

–

ns

D[X:0] Hold after Clock (K/K)

Output Times

tCO

tCHQV

K/K

Clock Rise to Data Valid

–

0.45

–

0.45

–

0.45

–

0.45

ns

tDOH

tCHQX

Data Output Hold after Output K/K

Clock Rise

–0.45

–

–0.45

–

–0.45

–

–0.45

–

ns

(Active to Active)

tCCQO

tCHCQV

K/K

Clock Rise to Echo Clock Valid

–

0.45

–

0.45

–

0.45

–

0.45

ns

tCQOH

tCHCQX

Clock Rise

–0.45

–

–0.45

–

–0.45

–

–0.45

–

ns

Echo Clock Hold after K/K

tCQD

tCQHQV

Echo Clock High to Data Valid

–

0.2

0.2

0.2

0.2

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.2

–

–0.2

–

–0.2

–

–0.2

–

ns

tCQH

tCQHCQL

HIGH[26]

Output Clock (CQ/CQ)

0.81

–

0.88

–

1.03

–

1.15

–

ns

t

t

CQ Clock Rise to

Clock Rise[26]

0.81

–

0.88

–

1.03

–

1.15

–

ns

CQ

CQHCQH

CQHCQH

(rising edge to rising edge)

t

t

Rise to High Z (Active to High Z)[27, 28]

–

0.45

–

0.45

–

0.45

–

0.45

ns

CHZ

Clock (K/K)

CHQZ

tCLZ

tCHQX1

Rise to Low Z[27, 28]

–0.45

–

–0.45

–

–0.45

–

–0.45

–

ns

Clock (K/K)

tQVLD

tQVLD

Echo Clock High to QVLD Valid[29]

–0.20

0.20

–0.20

0.20

–0.20

0.20

–0.20

0.20

ns

Notes

24.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

25.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated.

26.These parameters are extrapolated from the input timing parameters (tKHKH – 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.

27.tCHZ, tCLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady state voltage.

28.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

29.tQVLD spec is applicable for both rising and falling edges of QVLD signal.

Document Number: 001-06582 Rev. *D Page 23 of 29

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